Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/291,470, filed on 5/5/2021.
Information Disclosure Statement
The information disclosure statement(s) submitted on 4/8/2025, 4/11/2025 and 7/23/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim(s) 1-19 is/are objected to because of the following informalities:
Claim 1 is suggested to be amended as “wiring lines are included in the pixel region,” in line 4 on page 2 for addressing informalities.
Claims 2-19 are also objected for being dependent of the base claim.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. US 12302019 B2 (hereinafter “Pat’019”). Although the claims at issue are not identical, they are not patentably distinct from each other.
Instance Application
Pat’019
1. An imaging device, comprising:
a pixel region;
a first section including:
a first semiconductor substrate;
a first photoelectric conversion region disposed in the first semiconductor substrate;
a first floating diffusion coupled to the first photoelectric conversion region;
a first bonding portion;
a first wiring electrically connected between the first floating diffusion and the first bonding portion;
a second photoelectric conversion region disposed in the first semiconductor substrate;
a second floating diffusion coupled to the second photoelectric conversion region;
a second bonding portion;
a first transfer transistor that transfers charge from the first photoelectric conversion region to the first floating diffusion; and
one or more drive wiring lines electrically connected to the first transfer transistor;
a second section bonded to the first section via the first and second bonding portions and including readout circuitry coupled to the first bonding portion and the second bonding portion;
a third section bonded to the second section and including processing circuitry that processes signals from the readout circuitry; and
a wiring structure that electrically connects the processing circuitry to the one or more drive wiring lines, wherein, in a cross-sectional view, at least a portion of the one or more drive wiring lines are included in the pixel region wherein the wiring structure comprises:
a first electrode in the first section bonded to a second electrode in the second section; and
wiring that electrically connects the second electrode to the processing circuitry, and wherein the first electrode and the second electrode are outside the pixel region.
1. An imaging device, comprising:
[…a pixel region that includes a plurality of pixels…]
a first section including:
a first semiconductor substrate;
a first photoelectric conversion region disposed in the first semiconductor substrate;
a first floating diffusion coupled to the first photoelectric conversion region;
a first bonding portion;
a first wiring electrically connected between the first floating diffusion and the first bonding portion;
a second photoelectric conversion region disposed in the first semiconductor substrate;
a second floating diffusion coupled to the second photoelectric conversion region;
a second bonding portion;
a second wiring electrically connected between the second floating diffusion and the second bonding portion;
a third wiring electrically connected to a fixed voltage and that extends in a same direction as the first and second wirings at a location that is between the first wiring and the second wiring;
a first transfer transistor that transfers charge from the first photoelectric conversion region to the first floating diffusion; and
one or more drive wiring lines electrically connected to the first transfer transistor;
a second section bonded to the first section via the first and second bonding portions and including readout circuitry coupled to the first bonding portion and the second bonding portion;
a third section bonded to the second section and including processing circuitry that processes signals from the readout circuitry; and
a wiring structure that electrically connects the processing circuitry to the one or more drive wiring lines, wherein, in a cross-sectional view, the one or more drive wiring lines are within a pixel region that includes a plurality of pixels, wherein the wiring structure comprises:
a first electrode in the first section bonded to a second electrode in the second section; and
wiring that electrically connects the second electrode to the processing circuitry, wherein the first electrode and the second electrode are outside the pixel region, and wherein the readout circuitry comprises a first amplification transistor and a first selection transistor.
2. The imaging device of claim 1, wherein the readout circuitry comprises a first amplification transistor and a first selection transistor.
1… wherein the readout circuitry comprises a first amplification transistor and a first selection transistor.
3. The imaging device of claim 1, wherein the first section comprises:
a second wiring electrically connected between the second floating diffusion and the second bonding portion; and
a third wiring and that extends in a same direction as the first and second wirings at a location that is between the first wiring and the second wiring.
1… a second wiring electrically connected between the second floating diffusion and the second bonding portion;
a third wiring electrically connected to a fixed voltage and that extends in a same direction as the first and second wirings at a location that is between the first wiring and the second wiring;…
4. The imaging device of claim 3, wherein the third wiring is electrically connected to a fixed voltage.
1… a third wiring electrically connected to a fixed voltage…
5. The imaging device of claim 3, wherein the first section further comprises:
a first insulating layer, wherein the first wiring, the second wiring, and the third wiring are disposed in the first insulating layer, wherein the location is between the first wiring and the second wiring within the first insulating layer, wherein the third wiring penetrates a surface of the first insulating layer that is closest to the first semiconductor substrate; and
a second transfer transistor to transfer charge from the second photoelectric conversion region to the second floating diffusion.
2. The imaging device of claim 1, wherein the first section further comprises:
a first insulating layer, wherein the first wiring, the second wiring, and the third wiring are disposed in the first insulating layer, wherein the location is between the first wiring and the second wiring within the first insulating layer, wherein the third wiring penetrates a surface of the first insulating layer that is closest to the first semiconductor substrate; and
a second transfer transistor to transfer charge from the second photoelectric conversion region to the second floating diffusion.
6. The imaging device of claim 3, wherein the readout circuitry includes:
a first reset transistor, a first amplification transistor, and a first selection transistor electrically connected to the first bonding portion; and
a second reset transistor, a second amplification transistor, and a second selection transistor electrically connected to the second bonding portion.
3. The imaging device of claim 2, wherein the readout circuitry includes:
a first reset transistor, wherein the first reset transistor, the first amplification transistor, and the first selection transistor are electrically connected to the first bonding portion; and
a second reset transistor, a second amplification transistor, and a second selection transistor electrically connected to the second bonding portion.
7. The imaging device of claim 3, wherein the readout circuitry includes:
a first reset transistor and a first negative feedback circuit electrically connected to the first bonding portion; and
a second reset transistor and a second negative feedback circuit electrically connected to the second bonding portion.
4. The imaging device of claim 2, wherein the readout circuitry includes:
a first reset transistor and a first negative feedback circuit electrically connected to the first bonding portion; and
a second reset transistor and a second negative feedback circuit electrically connected to the second bonding portion.
8. The imaging device of claim 7, wherein the first and second negative feedback circuits each include an operational amplifier and a feedback capacitance.
5. The imaging device of claim 4, wherein the first and second negative feedback circuits each include an operational amplifier and a feedback capacitance.
9. The imaging device of claim 3, wherein the third wiring comprises a first opening in which the first wiring is disposed, and wherein the third wiring comprises a second opening in which the second wiring is disposed, and wherein the first section further comprises:
at least one insulating layer on the first semiconductor substrate, wherein the at least one insulating layer includes the first, second, and third wirings.
6. The imaging device of claim 1, wherein the third wiring comprises a first opening in which the first wiring is disposed, and wherein the third wiring comprises a second opening in which the second wiring is disposed, and wherein the first section further comprises:
at least one insulating layer on the first semiconductor substrate, wherein the at least one insulating layer includes the first, second, and third wirings.
10. The imaging device of claim 9, wherein the at least one insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer being closer to the second section than the first insulating layer and having a lower dielectric constant than the first insulating layer.
7. The imaging device of claim 6, wherein the at least one insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer being closer to the second section than the first insulating layer and having a lower dielectric constant than the first insulating layer.
11. The imaging device of claim 10, wherein the first section further comprises:
a third bonding portion, wherein the third wiring electrically connects to the third bonding portion, and wherein the first section and the second section are bonded via the first, second, and third bonding portions.
8. The imaging device of claim 7, wherein the first section further comprises:
a third bonding portion, wherein the third wiring electrically connects to the third bonding portion, and wherein the first section and the second section are bonded via the first, second, and third bonding portions.
12. The imaging device of claim 10, wherein the at least one insulating layer includes a third insulating layer on the second insulating layer and having a lower dielectric constant than the first insulating layer.
9. The imaging device of claim 7, wherein the at least one insulating layer includes a third insulating layer on the second insulating layer and having a lower dielectric constant than the first insulating layer.
13. The imaging device of claim 3, wherein the first section further comprises:
a first insulating layer, wherein the first wiring, the second wiring, and the third wiring are disposed in the first insulating layer, wherein the location is between the first wiring and the second wiring within the first insulating layer, and wherein the third wiring is coupled to a surface of the first insulating layer that is closest to the first semiconductor substrate, and wherein the second section further comprises:
a third bonding portion bonded to the first bonding portion; and
a fourth bonding portion bonded to the second bonding portion.
10. The imaging device of claim 1, wherein the first section further comprises:
a first insulating layer, wherein the first wiring, the second wiring, and the third wiring are disposed in the first insulating layer, wherein the location is between the first wiring and the second wiring within the first insulating layer, and wherein the third wiring is coupled to a surface of the first insulating layer that is closest to the first semiconductor substrate, and wherein the second section further comprises:
a third bonding portion bonded to the first bonding portion; and
a fourth bonding portion bonded to the second bonding portion.
14. The imaging device of claim 13, wherein the second section further comprises:
a fourth wiring that electrically connects the third bonding portion to the readout circuitry; and
a fifth wiring that electrically connects the fourth bonding portion to the readout circuitry.
11. The imaging device of claim 10, wherein the second section further comprises:
a fourth wiring that electrically connects the third bonding portion to the readout circuitry; and
a fifth wiring that electrically connects the fourth bonding portion to the readout circuitry.
15. The imaging device of claim 14, wherein the second section further comprises:
a sixth wiring electrically connected to the readout circuitry located between the fourth wiring and the fifth wiring.
12. The imaging device of claim 11, wherein the second section further comprises:
a sixth wiring electrically connected to the readout circuitry located between the fourth wiring and the fifth wiring.
16. The imaging device of claim 15, wherein the sixth wiring is aligned with the first wiring.
13. The imaging device of claim 12, wherein the sixth wiring is aligned with the first wiring.
17. The imaging device of claim 15, wherein the first section further comprises a fifth bonding portion, and wherein the second section further comprises a sixth bonding portion bonded to the fifth bonding portion.
14. The imaging device of claim 12, wherein the first section further comprises a fifth bonding portion, and wherein the second section further comprises a sixth bonding portion bonded to the fifth bonding portion.
18. The imaging device of claim 15, wherein the second section further comprises:
a second semiconductor substrate that includes the readout circuitry; and
an insulating layer on the second semiconductor substrate that includes the fourth, fifth, and sixth wirings.
15. The imaging device of claim 12, wherein the second section further comprises:
a second semiconductor substrate that includes the readout circuitry; and
an insulating layer on the second semiconductor substrate that includes the fourth, fifth, and sixth wirings.
19. The imaging device claim 1, wherein the processing circuitry is configured to provide a drive signal to the first transfer transistor, and wherein the drive signal travels from the processing circuitry through the second electrode, the first electrode, and the one or more drive wiring lines, in that order, to the first transfer transistor.
16. The imaging device of claim 1, wherein the processing circuitry is configured to provide a drive signal to the first transfer transistor, and wherein the drive signal travels from the processing circuitry through the second electrode, the first electrode, and the one or more drive wiring lines, in that order, to the first transfer transistor.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. U.S. Patent No. US 12302019 B2 (hereinafter “Pat’019”) in view of Kim et al (US 20180308895 A1).
Instance Application
Pat’019
20.
an imaging device, comprising:
a pixel region;
a first section including:
a first semiconductor substrate;
a first photoelectric conversion region disposed in the first semiconductor substrate;
a first floating diffusion coupled to the first photoelectric conversion region;
a first bonding portion;
a first wiring electrically connected between the first floating diffusion and the first bonding portion;
a second photoelectric conversion region disposed in the first semiconductor substrate;
a second floating diffusion coupled to the second photoelectric conversion region;
a second bonding portion;
a first transfer transistor that transfers charge from the first photoelectric conversion region to the first floating diffusion; and
one or more drive wiring lines electrically connected to the first transfer transistor;
a second section bonded to the first section via the first and second bonding portions and including readout circuitry coupled to the first bonding portion and the second bonding portion;
a third section bonded to the second section and including processing circuitry that processes signals from the readout circuitry; and
a wiring structure that electrically connects the processing circuitry to the one or more drive wiring lines, wherein, in a cross-sectional view, at least a portion of the one or more drive wiring lines are included in the pixel region, wherein the wiring structure comprises:
a first electrode in the first section bonded to a second electrode in the second section; and
wiring that electrically connects the second electrode to the processing circuitry, and wherein the first electrode and the second electrode are outside the pixel region.
1. An imaging device, comprising:
[…a pixel region that includes a plurality of pixels…]
a first section including:
a first semiconductor substrate;
a first photoelectric conversion region disposed in the first semiconductor substrate;
a first floating diffusion coupled to the first photoelectric conversion region;
a first bonding portion;
a first wiring electrically connected between the first floating diffusion and the first bonding portion;
a second photoelectric conversion region disposed in the first semiconductor substrate;
a second floating diffusion coupled to the second photoelectric conversion region;
a second bonding portion;
a second wiring electrically connected between the second floating diffusion and the second bonding portion;
a third wiring electrically connected to a fixed voltage and that extends in a same direction as the first and second wirings at a location that is between the first wiring and the second wiring;
a first transfer transistor that transfers charge from the first photoelectric conversion region to the first floating diffusion; and
one or more drive wiring lines electrically connected to the first transfer transistor;
a second section bonded to the first section via the first and second bonding portions and including readout circuitry coupled to the first bonding portion and the second bonding portion;
a third section bonded to the second section and including processing circuitry that processes signals from the readout circuitry; and
a wiring structure that electrically connects the processing circuitry to the one or more drive wiring lines, wherein, in a cross-sectional view, the one or more drive wiring lines are within a pixel region that includes a plurality of pixels, wherein the wiring structure comprises:
a first electrode in the first section bonded to a second electrode in the second section; and
wiring that electrically connects the second electrode to the processing circuitry, wherein the first electrode and the second electrode are outside the pixel region, and wherein the readout circuitry comprises a first amplification transistor and a first selection transistor.
But claim 1 of Pat’019 fails to teach
An electronic apparatus, comprising: a signal processing circuit; and an imaging device.
However, in the same field of endeavor Kim teaches
An electronic apparatus, comprising: a signal processing circuit (912); and an imaging device (900) (Fig. 7; para. 0064).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kim in claim 1 of Pat’019 to have an electronic apparatus, comprising: a signal processing circuit; and an imaging device for employing an electronic device including the image sensor to be a camera capable of taking a still image or a moving picture for storage or sharing yielding a predicted result.
Allowable Subject Matter
Claims 1 and 20 would be allowable if rewritten or timely filing a terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) to overcome the rejection(s) on the ground of nonstatutory double patenting, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoon et al (US 20200135791 A1): An image sensing apparatus includes a first substrate structure, a second substrate structure, and a memory chip. The first substrate structure includes a pixel region having a photoelectric conversion element. The second substrate structure includes a first surface connected to the first substrate structure and a second surface opposite the first surface, and also includes a circuit region to drive the pixel region. The memory chip is mounted on the second surface of the second substrate structure.
Hseih et al (US 20160165159 A1): a 3D stacked CMOS image sensor comprising a first substrate is identified as being the BSI sensor layer, a second substrate is identified as the analog front end (AFE) and analog digital conversion (ADC) layer, third substrate is identified as being the ISP/DSP, and fourth substrate is the PC board substrate (PCB).
Wan et al (US 20140042298 A1): A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit.
The prior art of record taken alone or in combination, fails to disclose or render obvious “a wiring structure that electrically connects the processing circuitry to the one or more drive wiring lines, wherein, in a cross-sectional view, at least a portion of the one or more drive wiring lines are included in the pixel region, wherein the wiring structure comprises: a first electrode in the first section bonded to a second electrode in the second section; and wiring that electrically connects the second electrode to the processing circuitry, and wherein the first electrode and the second electrode are outside the pixel region.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Quan Pham whose telephone number is (571)272-4438. The examiner can normally be reached Mon-Fri 9am-7pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571) 272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Quan Pham/Primary Examiner, Art Unit 2637
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