DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9-12, 16, 19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Fincato et al. (“Fincato”) (US Patent Application Publication No. 2015/0341119) in view of Islam et al. (“Islam”) (US Patent Application Publication No. 2021/0271020) and Welch et al. (“Welch”) (US Patent No. 7734191).
Regarding claim 1, Fincato discloses a system-in-package, comprising: a computing resource (fig. 3 each of elements ICn and paragraph 0028 in light of paragraph 0012, where “system chips” that communicate to each other over photonic links at 10 Gbps rates read on computing resources); and an interface associated with the computing resource (fig. 3 elements 12-14 and paragraph 0028), the interface comprising: a first transmit unit for sending data from the computing resource via a first optical link (fig. 4 elements 1 and 9 and paragraph 0030 in light of fig. 2 element 4 and paragraph 0027), wherein the first transmit unit comprises a driver connected to a modulator (fig. 2 element 10 and paragraph 0027), and a first receive unit (fig. 2 element 6 and paragraph 0027) for receiving data sent to the computing resource via a second optical link, wherein the first receive unit comprises a photodetector (fig. 2 element 9, two links for bidirectionality).
Fincato discloses a TIA for the receiver (paragraph 0027) but does not disclose a serializer, the driver being connected to the serializer, wherein the serializer provides an output to the driver, and a deserializer. Islam discloses a related optical interposer with a SERDES interfacing with the circuits connected to the optical interposer (fig. 19 and paragraph 0057). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include SERDES functionality with each of the bidirectional EICs of Fincato, the serialize output going into the modulator driver, and the TIA output going into the deserializer, since SERDES operation allows a single photonic link to interconnect circuits with parallel and/or plural data lines.
Also, Fincato discloses the EIC with the driver bonded to a PIC (fig. 4), and thus does not disclose the driver in a PIC. Welch discloses a modulator driver in a PIC (fig. 4A element 401 and col. 6 line 56 to col. 7 line 49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate the driver for the PIC of Fincato, in light of Welch, to provide the benefit of fabricating transmitter components on the same substrate.
Regarding claim 2, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the first optical link comprises a first waveguide from the modulator to a second receive unit associated with a second computing resource (Fincato: fig 1 elements 4 coupled to elements 6 via waveguides 8 and 9 and paragraphs 0028-0033).
Regarding claim 3, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 2 wherein the second optical link comprises a second waveguide from a second transmit unit associated with the second computing resource to the photodetector (fig. 1 elements 4 coupled to elements 6 via waveguides 8 and 9 and paragraphs 0028-0033, bidirectional transmission).
Regarding claim 4, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 3, further comprising a third transmit unit for sending data from the computing resource via a third optical link wherein the first transmit unit comprises a second driver connected to a second modulator, and a second serializer, wherein the third optical link comprises an optical pathway that uses an optical interface that guides light from a waveguide into a fiber (Fincato: fig. 3, each ICn has plural bidirectional modulator/photodetector pairs for communicating with plural other ICs).
Regarding claim 6, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the computing resource is one or more of a memory element or a processing element (Fincato: fig. 3 each of elements ICn and paragraph 0028 in light of paragraph 0012, where “system chips” that communicate to each other over photonic links at 10 Gbps rates read on processing elements).
Regarding claim 9, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the serializer converts an electronic message received in a form of parallel data into a signal suitable for driving the modulator, and wherein the deserializer converts a received message back into parallel data (Islam: fig. 19 and paragraph 0057, as applicable for the combination).
Regarding claim 10, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the modulator is selected from the group consisting of an electro-absorption modulator (EAM), a micro-ring resonator, a ring modulator, a Mach-Zehnder interferometer (MZI), and a quantum confined stark effect (QCSE) electro-absorptive modulator (Fincato: paragraph 0023).
Regarding claim 11, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, but as formulated above does not disclose that the computing resource is one or more of a NAND Flash memory, a solid-state drive (SSD) memory, a NOR Flash memory, a CMOS memory, a thin film transistor-based memory, a phase change memory (PCM), a storage class memory (SCM), a magneto-resistive memory (MRAM), a resistive RAM, a DRAM, an HBM, a DDR-based DRAM, or a DIMM memory. Islam also discloses that the optical interposer can be used as an inter-device communication solution for a finite number of identified, predictable device types that include DRAM, SRAM or another type of memory (fig. 19 and paragraph 0055). From Islam, one skilled in the art could have pursued using optical interposer with relatively high bandwidth memory with a reasonable expectation of successfully communicating between devices via the interposer. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try using the optical interposer of the combination with various memory types, as an inter-device communication solution for memories as taught by Islam, since there is a reasonable expectation of success for communicating between devices via the interposer.
Regarding claim 12, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, and discloses that the computing resource includes a processing element that provides access to compute traffic (fig. 3 each of elements ICn and paragraph 0028 in light of paragraph 0012, where “system chips” that communicate to each other over photonic links at 10 Gbps rates read on computing resources) but as formulated above does not also disclose that the computing resource includes a combination of the processing element and at least one memory element that provides access to memory traffic. Islam also discloses that the optical interposer can be used as an inter-device communication solution for a finite number of identified, predictable device types that include DRAM, SRAM or another type of memory (fig. 19 and paragraph 0055). From Islam, one skilled in the art could have pursued using optical interposer with relatively high bandwidth memory with a reasonable expectation of successfully communicating between devices via the interposer. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try using the optical interposer of the combination between system chips and various memory types, as an inter-device communication solution for memories as taught by Islam, since there is a reasonable expectation of success for communicating between devices via the interposer, and providing the benefit of supplemental or additional memory for the system chips.
Regarding claim 16, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the interface further comprises at least one additional transmit unit for sending data from the computing resource via a first one or more additional optical links of a bidirectional channel and at least one additional receive unit for receiving data sent to the computing resource via a second one or more additional optical links of the bidirectional channel (fig. 1 elements 4 coupled to elements 6 via waveguides 8 and 9 and paragraphs 0028-0033, bidirectional transmission and fig. 3, each ICn has plural bidirectional modulator/photodetector pairs for communicating with plural other ICs).
Regarding claim 19, Fincato discloses a system-in-package, comprising: a first computing resource, a second computing resource, and a fabric coupled to the first computing resource and the second computing resource (fig. 3 each of elements ICn and 14 and paragraph 0028 in light of paragraph 0012, where “system chips” that communicate to each other over photonic links at 10 Gbps rates read on computing resources), the fabric comprising: a first interface associated with the first computing resource (fig. 3 elements 12-14 and paragraph 0028, for IC1), the first interface comprising: a first transmit unit for sending data from the first computing resource via a first optical link of a bidirectional channel (fig. 4 elements 1 and 9 and paragraph 0030 in light of fig. 2 element 4 and paragraph 0027, for IC1), the first transmit unit comprising a first driver connected to a first modulator (fig. 2 element 10 and paragraph 0027, for IC1), the first modulator being implemented in a photonic integrated circuit (PIC) (fig. 4 element 1 and paragraphs 0023 and 0027, for IC1), and a first receive unit (fig. 2 element 6 and paragraph 0027, for IC1) for receiving data sent to the first computing resource via a second optical link of the bidirectional channel, the first receive unit comprising a photodetector in the PIC (fig. 2 element 9, two links for bidirectionality, for IC1); and a second interface associated with the second computing resource (fig. 3 elements 12-14 and paragraph 0028, for IC2), the second interface comprising: a second transmit unit for sending data from the second computing resource via the second optical link of the bidirectional channel (fig. 4 elements 1 and 9 and paragraph 0030 in light of fig. 2 element 4 and paragraph 0027, for IC2), the second transmit unit comprising a second driver connected to a second modulator (fig. 2 element 10 and paragraph 0027, for IC2), the second modulator being implemented in the PIC (fig. 4 element 1 and paragraphs 0023 and 0027, for IC2); and a second receive unit (fig. 2 element 6 and paragraph 0027, for IC2) for receiving data sent to the second computing resource via the first optical link of the bidirectional channel, the second receive unit comprising a second photodetector in the PIC (fig. 2 element 9, two links for bidirectionality).
Fincato discloses a TIA for the receiver (paragraph 0027) but does not disclose for each computing resource, a serializer in a first electronic integrated circuit (EIC), the driver being connected to the serializer, wherein the serializer provides an output to the driver, and a deserializer in the EIC. Islam discloses a related optical interposer with a SERDES interfacing with the circuits connected to the optical interposer (fig. 19 and paragraph 0057). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include SERDES functionality with each of the bidirectional EICs of Fincato, the serialize output going into the modulator driver, and the TIA output going into the deserializer, since SERDES operation allows a single photonic link to interconnect circuits with parallel and/or plural data lines.
Also, Fincato discloses the EIC with the driver bonded to a PIC (fig. 4), and thus does not disclose the driver in a PIC. Welch discloses a modulator driver in a PIC (fig. 4A element 401 and col. 6 line 56 to col. 7 line 49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate the driver for the PIC of Fincato, in light of Welch, to provide the benefit of fabricating transmitter components on the same substrate.
Regarding claim 21, the combination of Fincato and Islam discloses the system-in-package of claim 19, wherein each computing resource of the first computing resource and the second computing resource is one or more of a memory element or a processing element (Fincato: fig. 3 each of elements ICn and paragraph 0028 in light of paragraph 0012, where “system chips” that communicate to each other over photonic links at 10 Gbps rates read on processing elements).
Regarding claim 22, the combination of Fincato and Islam discloses the system-in-package of claim 19, wherein each modulator of the first modulator and the second modulator is selected from the group consisting of an electro-absorption modulator (EAM), a micro-ring resonator, a ring modulator, a Mach-Zender interferometer (MZI), and a quantum confined stark effect (QCSE) electro-absorptive modulator (Fincato: paragraph 0023).
Regarding claim 23, the combination of Fincato and Islam discloses the system-in-package of claim 19, but as formulated above does not disclose that each computing resource of the first computing resource and the second computing resource is one or more of a NAND Flash memory, a solid-state drive (SSD) memory, a NOR Flash memory, a CMOS memory, a thin film transistor-based memory, a phase change memory (PCM), a storage class memory (SCM), a magneto-resistive memory (MRAM), a resistive RAM, a DRAM, an HBM, a DDR-based DRAM, or a DIMM memory. Islam also discloses that the optical interposer can be used as an inter-device communication solution for a finite number of identified, predictable device types that include DRAM, SRAM or another type of memory (fig. 19 and paragraph 0055). From Islam, one skilled in the art could have pursued using optical interposer with relatively high bandwidth memory with a reasonable expectation of successfully communicating between devices via the interposer. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try using the optical interposer of the combination with various memory types, as an inter-device communication solution for memories as taught by Islam, since there is a reasonable expectation of success for communicating between devices via the interposer.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fincato (US Patent Application Publication No. 2015/0341119) in view of Islam (US Patent Application Publication No. 2021/0271020) and Welch (US Patent No. 7734191), as applicable for claim 1, and further in view of Li et al. (“Li”) (US Patent Application Publication No. 2019/0089466).
Regarding claim 18, the combination of Fincato, Islam and Welch discloses the system-in-package of claim 1, wherein the first receive unit further comprises: a gain control to normalize a signal level of a signal containing the data sent to the computing resource via the second optical link (Fincato: paragraph 0027, the TIA reads on gain control to normalize a signal level), but does not disclose a slicer to extract a bit-stream that is provided as an input to a de-serializer for converting the data sent to the computing resource into parallel data. However, using a slicer after a TIA is conventional for an optical receiver, for bit recovery. Li shows slicing after TIA in an optical receiver (fig. 1 and paragraphs 0014-0016). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a slicer after the TIA of the combination, to detect symbol timing in the received signal for data recovery.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments of 3 November 2025 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN M CORS whose telephone number is (571)272-3028. The examiner can normally be reached Monday-Friday.
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/NATHAN M CORS/Primary Examiner, Art Unit 2634