Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 04/07/2025. Claims 1 -20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 1-6, 8-9 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinugasa U.S. patent No. 6,469,647.
Regarding claim 1. Fig. 1 of Kinugasa discloses a circuit (col. 2 lines 13-15) comprising: a first digital-to-analog converter (D-A 108) comprising a set of resistors connected in series (series of R0…R31) , the set of resistors (R0…R31) connected to a multiplexor (132) a first resistor (R31) of the set of resistors (R0…R31) connected to a positive reference voltage (VRT) of the circuit (Fig. 1) and a second resistor(R0) of the set of resistors (R0…R31) connected to a negative reference voltage of the circuit (VRB) , an output of the circuit (300) providing a reference voltage (Vout); a second DAC (Low-Oder D-A 200) comprising a set of R-2R resistors (R2R) , the set of R-2R resistors (R2R) comprising a first resistor with a value R (R) and a second resistor with a value 2R (2R) , the value R (value of R) being half the value 2R (2R) ; and a scaling circuit (right most 2R at terminal 13) to modify a resolution (eight bits resolution of D-A 200; D0…D7) of the second DAC (low order bits D0…D7) relative to a resolution (5 bits resolution Col. 3 lines 21-22) of the first DAC (high order bits of D-A 100), the scaling circuit (scaling by right most 2R at terminal 13) connecting the first DAC to the second DAC (Low-Oder D-A 200).
Regarding claim 2. The circuit of claim 1, Fig. 1 further discloses wherein the scaling circuit (right most 2R at node 13) is connected to an output (output 11, 12) the multiplexor (102), an output of the second DAC (output 200), and the output of the circuit (300).
Regarding claim 3. The circuit of claim 1, Fig. 1 further discloses wherein the scaling circuit comprises a scaling resistor (right most 2R at node 13), a value of the scaling resistor (right most 2R at node 13) being based on at least one of (a) an effective impedance of the set of resistors (impedance of R0…R31) of the first DAC (108) , (b) an effective impedance of the multiplexor (impedance of 102) of the first DAC (108) , (c) an effective impedance of one or more reference switches of the second DAC (effective impedance switches of 202) , or (d) a quotient determined from the value 2R (value 2R of 200) and a number of bits (high order bits of D-A 108; Col. 3 lines 21-22) associated with the first DAC (108).
Regarding claim 4. The circuit of claim 1, Fig. 1 further discloses wherein the scaling circuit resistor right most 2R at node 13) comprises a scaling resistor with the value 2R (right most 2R value at node 13) and at least one R-2R pair (R2R pair of 200) of scaling resistors (right most 2R at node 13) connected to the output of the second DAC (108).
Regarding claim 5. The circuit of claim 1, Fig. 1 further discloses wherein the set of resistors (R0…R31) of the first DAC (108) are of a same type of resistor and of a same value of resistor (same value of R0…R31; Col. 3 lines 26-29).
Regarding claim 6. The circuit of claim 1, Fig. 1 further discloses wherein a value of a resistor (value of each R…R310) of the set of resistors (of R0…R31; Col. 3 lines 26-29) of the first DAC (108) is set to the value R (R)from the second DAC (R of 200).
Regarding claim 8. The circuit of claim 1, Figs. 1 and 2 further disclose wherein: an input (D12…D0) of the circuit comprises a binary code (D12…D8) , the first DAC (108) is associated with M coarse bits of the binary code (most significant bits MSB), the M coarse bits including a most significant bit of the binary code (D11…D8) , and the second DAC (108) is associated with N fine bits of the binary code (D7….D0 low order bits ), the N fine bits (low-order bits) including a least significant bit of the binary code (D0) , M and N being positive integers (5 bits of D12…D8 and 8 bits of D7…D0) ) , M (5 bits D12…D8) being less than (8 bits of D7…D0)
Regarding claim 9. The circuit of claim 1, Fig. 1 further discloses wherein the second resistor of the set of R-2R resistors (R2R of 200) is connected to a reference switch (202) that switches between the positive reference voltage (VRT) and the negative reference voltage (VRT).
Regarding claim 17. Fig. 1 of Kinugasa discloses a device comprising: a digital-to-analog converter (DAC) circuit (Fig. 1) configured to output a reference voltage (Vout) for an operation of the device (Fig. 1) , the DAC circuit (Fig. 1) comprising :a first DAC (100) comprising a set of resistors connected in series (101) , the set of resistors (101) connected to a multiplexor (102, 103), a first resistor (first resistor of 101) of the set of resistors (101) connected to a positive reference voltage (VRT) of the circuit (100, 200) and a second resistor (second resistor of 102) of the set of resistors (101) connected to a negative reference voltage (VRB) of the circuit; (100, 200); a second DAC (200) comprising a set of R-2R resistors (201) , the set of R-2R resistors (201) comprising a first resistor with a value R (R) and a second resistor with a value 2R (2R) , the value R (R) being half the value 2R (2R) ; and a scaling circuit (right most 2R at node 13) to modify a resolution (eight bits resolution of D-A 200; D0…D7) of the second DAC (200) relative to a resolution (5 bits resolution Col. 3 lines 21-22) of the first DAC (100) , the scaling circuit (scaling by right most 2R at terminal 13) connecting the first DAC (100) to the second DAC (200) .
Regarding claim 18. The device of claim 17, wherein the scaling circuit (scaling by right most 2R at terminal 13) is connected to an output (11, 12) of the multiplexor (102, 103), an output (output of 201) of the second DAC (200), and the output (Vout) of the circuit (Fig. 1)
Regarding claim 19. The device of claim 17, Fig. 1 further discloses wherein the scaling circuit (scaling by right most 2R at terminal 13) comprises a scaling resistor (scaling by right most 2R at terminal 13), a value of the scaling resistor (2R) being based on the value 2R (2R).
5. Claims 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang U.S. patent No. 10,305,505.
Fig. 1 of Zhang discloses a circuit (108) comprising DAC circuit 108 having a resistor string DAC 194 (see Fig. 5A for disclose diagram of 194) and a R2R DAC 192 (see Fig. 3 and Fig. 7 for discloses a diagram of 192 comprising first and second R2R networks).
Regarding claim 10. Fig. 1, Fig. 3 Fig. 5A , Fig. 7 of Zang discloses a circuit (108) comprising: a first digital-to-analog converter (194) comprising a set of resistors connected in series (502 in Fig. 5A), a first resistor (first 1/R in Fig. 5 A) of the set of resistors (502 in Fig. 5A) connected to a multiplexor (504 in Fig. 5A) and a second resistor (second 1/R in Fig. 5A) of the set of resistors (502 in Fig. 5A) connected to the multiplexor (504); a second DAC (first R2R network connected of output 136H in Fig. 3) comprising a first set of R-2R resistors (R2R network of 136H in Fig. 3) , the first set of R-2R resistors (R2R network of 136H in Fig. 3) comprising a first R resistor with a value R (1R in Fig. 3) and a first 2R resistor with a value 2R (2R in Fig. 3), the first resistor (first 1/R in Fig. 5A) of the set of resistors (502 in Fig. 5A) being connected to an output (output 136H in Fig. 3 and Fig. 5A) of the second DAC (first R2R network connected of 136H in Fig. 3); a third DAC (second R2R network connected of output 136L in Fig. 3) comprising a second set of R-2R resistors (second R2R network connected of 136L in Fig. 3), the second set of R-2R resistors (second R2R network connected of 136L in Fig. 3) comprising a second R resistor with the value R (1R of second R2R network connected of 136L in Fig. 3) and a second 2R resistor with the value 2R (2R of second R2R network connected of 136L in Fig. 3), the value R (1R in Fig. 3) being half the value 2R (2R in Fig. 3), the second resistor of the set of resistors (second R-2R network connected of 136L in Fig. 3 ) being connected to an output (output 136L in Fig. 3) of the third DAC (second R2R network connected of 136L in Fig. 3); a termination resistor (2R) of the second DAC (first R2R network connected of 136H in Fig. 3) connected (144) to a positive reference voltage (134H see Fig. 1 for discloses 134H is a VrefH) of the circuit (108); and a termination resistor (2R) of the third DAC (second R2R network connected of 136L in Fig. 3) connected to a negative reference voltage((134L see Fig. 1 for discloses 134L is a VrefL) of the circuit (108) , an output of the circuit providing a reference voltage (VOUT).
Regarding claim 11. The circuit of claim 10, Fig. 1, Fig. 3 Fig. 5A further disclose wherein: the first DAC (Fig. 5) receives an output (136H Fig. 5A) the second DAC (first R2R network connected output 136H in Fig. 3) and an output (136L in Fig. 5A) of the third DAC (second R2R network connected output 136L in Fig. 3), and an output (146 in Fig. 5A) of the multiplexor (504 in Fig. 5A) provides the output (VOUT) of the circuit (108).
Regarding claim 12. The circuit of claim 10, Fig. 1(first and second R2R networks in Fig. 3further disclose wherein the set of resistors of the first DAC (502 in Fig. 5) are of a same type of resistor and of a same value of resistor (1/2 R).
Regarding claim 13. The circuit of claim 10, Fig. 1, Fig. 3 Fig. 5A further disclose wherein a value of a resistor (1/2 R in Fig. 5A) of the set of resistors (502 in Fig. 5A) of the first DAC (194) is set to the value R (1R in Fig. 3) from the second DAC or the third DAC (first and second R2R networks in Fig. 3).
Regarding claim 14. The circuit of claim 10, Fig. 1, Fig. 3 Fig. 5A further disclose wherein a value of a resistor (1/2 R in Fig. 5A) of the set of resistors (502 in Fig. 5A) of the first DAC (194) is different from the value R (1R) from the second DAC or the third DAC (first and second R2R networks in Fig. 3).
Regarding claim 15. The circuit of claim 10, Fig. 1 and Fig. 3 and Fig. 5A further disclose wherein: an input of the circuit (108) comprises a binary code (dacm<8>…..dacm<4>), the first DAC (194) is associated with M coarse bits (Col. 1 lines of the binary code (dacm<6>….. dacm<4>), the M coarse bits (dacm<8>…..dacm<6>) including a most significant bit of the binary code (Col. 3 lines 58-67), and the second DAC and the third DAC (first and second R2R network of Fig. 3) are associated with N fine bits (dacm<8>…..dacm<4>) of the binary code (Col. 3 lines 58-67), the N fine bits (dacm<8>…..dacm<6>) including a least significant bit of the binary code (Col. 3 lines 58-67), M (dacm<6>….. dacm<4>) and N (dacm<8>…..dacm<6>) being positive integers, M (dacm<6>….. dacm<4>) being equal to N (dacm<8>…..dacm<6>).
Regarding claim 16. The circuit of claim 10, Fig. 1 and Fig. 3 and Fig. 5A further discloses wherein the first 2R resistor of the second DAC (first 2R of R2R network connected of 136H in Fig. 3) is connected to a reference switch (switching of Reference 134H, 1434L in Fig. 3) that switches between the positive reference voltage and the negative reference voltage (134H and 134L; see Fig. 1 for discloses 134H is a VrefH and 134L is VrefL).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kinugasa applied to claim 6 above in view of Zhang U.S. patent No. 10,305,505.
Fig. 1 of Kinugasa applied to claim 6 above does not disclose a value of a resistor of the set of resistors (of the first DAC 100) is different from the value R from the second DAC (200).
Fig. 3 and Fig. 5A of Zhang discloses an DAC device (192, 194) discloses a value of a resistor (1/2R in Fig. 5) of the set of resistors (502 in Fig. 5A) is different from the value R (R in Fig. 3) from the second DAC (192).
Kinugasa and Zhang are common subject matter of reference resistor network of DAC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Zhang into Kinugasa for the purpose of providing High DAC accuracy is desirable in many applications, such as medical devices, optical devices industrial control products, display drivers, etc. Higher accuracy DACs typically occupy significant circuit area, and increased bit accuracy generally results in significant increases in the number of switches and resistor elements. In addition, more calibration memory and calibration time are required for DAC circuits that provide high bit accuracy (Col. 3 lines 10-18 of Zhang).
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kinugasa applied to claim 17 above in view of Downey et al. Pub. No. 2015/0097712.
Kinugasa applied to claim 17 above does not discloses wherein the device comprises a memory device, the device being configured to determine whether a memory cell of the device stores a logical 1 or a logical 0 based on the reference voltage.
Fig. 12 of Downey et al. discloses a DAC device, the device comprises a memory device (Correction Code look up 74, 76), the device (Fig. 12) being configured to determine (Decoder 72) whether a memory cell (Fig. 11) of the device stores (Correction Code look up 74, 76) a logical 1 or a logical 0 (Fig. 11) based on the reference voltage (Vout 57).
Kinugasa and Downey et al. are common subject matter of reference resistor network of DAC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Downey et al. into Kinugasa for the purpose of providing a memory for storing information relating to components mismatched in the DAC. The memory may be any suitable volatile and/or non-volatile memory. The value of individual components or error values associated with components may be stored in a look-up table (paragraph 0013 of Downey et al.).
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/08/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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