DETAILED ACTION
Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the following: the arrangement structure of the image sensor according to claim 8, wherein each of the pixel units further comprises a gain module and/or a fast reset module, wherein the gain module and/or the fast reset module are arranged in the same area as the reset module and the readout module; wherein the gain module comprises a gain transistor, and the fast reset module comprises a fast reset transistor.
Based on the claim as currently constructed, it is unclear what is being claimed based on the wording of the. The claim as constructed is comprised of “and/or” regarding the gain module and fast reset module, however in the last recitation of the claim, requires the gain module and the fast reset module? Corrective action is required immediately. The claim needs to be clarified to determine is it the gain module, fast reset module, or both modules. Claim 17 depends from claim 16, and is rejected based on the same reasoning/rationale. Claim 17 claims both the gain module and fast reset module, however, claim 16 claims either the gain module or the fast reset module.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-11, 13 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Torii et al (US 2024/0334082 A1).
As per claim 1, Torii discloses an image sensor (fig. 1, imaging element 10), comprising multiple pixel units arranged in an array (fig. 1, imaging element 10, pixel array unit 11), wherein each of the pixel units (fig. 1, imaging element 10, pixel array unit 11, pixel 20) comprises:
M photosensitive modules (fig. 4, pixel 20A, PD1-PD4) coupled to a floating diffusion node (fig. 4, pixel 20A, FD 21), wherein the M photosensitive modules are configured to convert optical signals into first charge signals and second charge signals, and to store the first charge signals and transfer the first charge signals to the floating diffusion node (fig. 4, pixel 20A, charges from PD1-PD4 are transferred to FD 21, and second charges of OFG1-OFG4 are second charges (i.e. overflow charges) from PD1-PD4);
M overflow modules (fig. 4, pixel 20A, OFG1-OFG4), respectively coupled to the M photosensitive modules (fig. 4, pixel 20A, OFG1-OFG4, coupled to PD1-PD4 respectively), wherein the M overflow modules are configured to store the second charge signals (fig. 4, pixel 20A, OFG1-OFG4 charges may be stored in FDC1-FDC4 respectively);
M transfer modules (fig. 4, pixel 20A, TRG1-TRG4), coupled between the floating diffusion node (fig. 4, pixel 20A, FD 21) and the M overflow modules (fig. 4, pixel 20A OFG1-OFG4), wherein the M transfer modules are configured to transfer the second charge signals to the floating diffusion node (fig. 4, pixel 20A, TRG1-TRG4 are configured to transfer OFG1-OFG4 charges to FD 21); wherein M is a natural number greater than or equal to 2 (fig. 4, pixel 20A, TRG1-TRG4 is greater than 2);
a reset module (fig. 4, pixel 20A, RST 27), coupled to the floating diffusion node, wherein the reset module is configured to reset at least the floating diffusion node and the photosensitive modules (para 0047);
a readout module, coupled to the floating diffusion node, wherein the readout module is configured to perform quantitative readout of the first charge signals and the second charge signals (fig. 4, pixel 20A, column signal line 17, coupled to FD 21, para 0036-0039).
As per claim 2, Torii further discloses the image sensor according to claim 1, wherein each of the pixel units (fig. 4, pixel 20A) further comprises:
a gain module (fig. 4, pixel 20A, dual gain conversion DGC1-DGC4), wherein the gain module is coupled between the reset module and the floating diffusion node, or coupled to the floating diffusion node (fig. 4, pixel 20A, FD 21), wherein the gain module is configured to switch between different conversion gains (fig. 4, pixel 20A, DGC1-DGC4, may switch between a high and low state, para 0050);
and/or, a fast reset module, coupled to the M overflow modules, wherein the fast reset module is configured to fast reset the overflow modules (limitation above has been met, therefore claim limitations as a whole has been met).
As per claim 3, Torii further discloses the image sensor according to claim 2, wherein each of the pixel units comprises the gain module and the gain module is coupled between the reset module and the floating diffusion node, wherein the gain module comprises a gain transistor, wherein a control terminal of the gain transistor receives a gain control signal, wherein a first terminal of the gain transistor is coupled to the reset module, and a second terminal of the gain transistor is coupled to the floating diffusion node; wherein each of the pixel units comprises the gain module and the gain module is coupled to the floating diffusion node, and the gain module comprises the gain transistor and a gain capacitor, wherein a control terminal of the gain transistor receives a gain control signal, wherein a first terminal of the gain transistor is coupled to the floating diffusion node, and a second terminal of the gain transistor is coupled to a first potential through the gain capacitor; wherein each of the pixel units comprises the fast reset module, and the fast reset module comprises a fast reset transistor, wherein a control terminal of the fast reset transistor receives a fast reset signal, wherein a first terminal of the fast reset transistor is coupled to a second potential, and a second terminal of the fast reset transistor is coupled to each of the overflow modules;
and/or, wherein each of the pixel units (fig. 4, pixel 20A) comprises the gain module (fig. 4, pixel 20A, DGC1-DGC4), and there is a connection structure between gain modules of two or more pixel units, to realize sharing among the gain modules based on the connection structure (fig. 4, pixel 20A, DGC1-DGC4, are gain modules shared between multiple pixels, lastly claim limitations has been met based on and/or limitation).
As per claim 4, Torii further discloses the image sensor according to claim 3, wherein each of the pixel units comprises the gain module, and the gain module further comprises a gain node, wherein one or more of the M transfer modules are coupled between the gain node and the corresponding overflow module; wherein the gain module is coupled between the reset module and the floating diffusion node, and the first terminal of the gain transistor acts as a gain node; or wherein the gain module is coupled to the floating diffusion node, and the second terminal of the gain transistor acts as a gain node (fig. 4, pixel 20A, DGC1-DGC4 are coupled to FD 21, and other end of DGC1-DGC4 is a dual gain node, lastly limitations has been met based on “or” limitation).
As per claim 5, Torii further discloses the image sensor according to claim 1, wherein each of the overflow modules comprises an overflow transistor and an overflow capacitor, wherein a control terminal of the overflow transistor receives an overflow control signal, wherein a first terminal of the overflow transistor is coupled to a corresponding photosensitive module, and a second terminal of the overflow transistor is coupled to a third potential through the overflow capacitor; wherein each of the pixel units comprises the fast reset module, and the second terminal of the overflow transistor is changed from being coupled to the third potential to being coupled to the fast reset module through the overflow capacitor;
and/or, the transfer module comprises a transfer transistor (fig. 4, pixel 20A, TRG1-TRG4 is a transfer transistor, wherein a control terminal of the transfer transistor receives a transfer control signal, wherein a first terminal of the transfer transistor is coupled to a corresponding overflow module (fig. 4, pixel 20A, TRG1-TRG4, one end is coupled to OFG1-OFG4), and a second terminal of the transfer transistor is coupled to the floating diffusion node (fig. 4, pixel 20A, TRG1-TRG4, other end is coupled to FD 21); wherein one or more of the M transfer modules are coupled between the gain node and the corresponding overflow module (fig. 4, pixel 20A, TRG1-TRG4, is coupled between DGC1-DGC4 and OFG1-OFG4), and the second terminal of the transfer transistor in the corresponding transfer module is changed from being coupled to the floating diffusion node to being coupled to the gain node (fig. 4, pixel 20A, is further connected to DGC1-DGC4, claim limitation as a whole has been met due to and/or limitation).
As per claim 8, Torii further discloses an arrangement structure of an image sensor according to claim 1, wherein each of the pixel units (fig. 4, pixel 20A) comprises:
a first area, wherein the photosensitive modules are arranged in the first area (fig. 4, pixels 20A, PD1-PD4 arranged in a first area);
a second area defined in the first area, wherein the floating diffusion node is arranged in the second area (fig. 4, pixels 20A, FD21 is arranged in second area);
wherein in each of the pixel units, the overflow modules and transfer modules are arranged in the first area and are arranged respectively around the photosensitive modules (fig. 4, pixels 20A, OFG1-OFG4 and TRG1-TRG4 are arranged around PD1-PD4 in the first area);
wherein in each of the pixel units, the reset module and the readout module are arranged in the second area or arranged around the first area (fig. 4, pixels 20A, RST 27, column signal line 17 is arranged in second area).
As per claim 9, Torii further discloses the arrangement structure of the image sensor according to claim 8, wherein in each of the pixel units, the photosensitive modules are arranged in 2*1 or 2*2 arrays depending on a number of the photosensitive modules in the first area, wherein M is a natural number greater than or equal to 2 and less than or equal to 4; wherein the second area is defined in the first area based on the photosensitive modules (fig. 4, pixels 20A, arranged in a 2 by 2 array, and TRG1-TRG4 is greater than 2).
As per claim 10, Torii further discloses the arrangement structure of the image sensor according to claim 8, wherein each of the photosensitive modules comprises the photosensitive element and the transmission transistor (fig. 4, pixels 20A, PD1-PD4, TRG1-TRG4), wherein the transmission transistor is arranged in a first corner area of the corresponding photosensitive element (fig. 4, pixels 20A, TRG1-TRG4 are arranged in a corner); wherein the second area is defined based on an outer edge of each transmission transistor; and/or, each of the overflow modules comprises the overflow transistor, wherein the overflow transistor is arranged next to an edge or corner of the corresponding photosensitive element (fig. 4, pixels 20A, OFG1-OFG4, is arranged next to PD1-PD4); and/or, each of the transfer modules comprises the transfer transistor, wherein the transfer transistor is arranged on the outside of the corresponding photosensitive element (claim limitations have been met based on and/or clause in limitations).
As per claim 11, Torii further discloses the arrangement structure of the image sensor according to claim 10, wherein each of the transfer modules comprises the transfer transistor, wherein each transfer transistor is arranged adjacent to the corresponding overflow transistor, and each transfer transistor is arranged on an outer edge of each overflow transistor in a clockwise rotation manner (fig. 4, pixels 20A, TRG1-TRG4 are arranged adjacent to OFG1-OFG4 on an outer edge clockwise).
As per claim 13, Torii further discloses the arrangement structure of the image sensor according to claim 10, wherein each overflow transistor is arranged in a second corner area of the corresponding photosensitive element, wherein the second corner area is arranged opposite to the first corner area (fig. 4, pixels 20A, OFG1-OFG4, arranged in a second corner corresponding to PD1-PD4, opposite a first corner); or, each overflow transistor is arranged in a third corner area of the corresponding photosensitive element, wherein the third corner area is arranged along a first direction or a second direction opposite the first corner area (claim limitations have been met based on and/or clause in limitations).
As per claim 16, Torii further discloses the arrangement structure of the image sensor according to claim 8, wherein each of the pixel units further comprises a gain module (fig. 4, pixels 20A, DGC1-DGC4) and/or a fast reset module, wherein the gain module and/or the fast reset module are arranged in the same area as the reset module and the readout module (fig. 4, pixels 20A, DGC1-DGC4, in same area as RST 27 and column signal line 17); wherein the gain module comprises a gain transistor (fig. 4, pixels 20A, DGC1-DGC4 consists of transistors), and the fast reset module comprises a fast reset transistor (claim limitations have been met based on and/or construction of limitations, also see 112b rejection above regarding gain module and fast reset module).
Allowable Subject Matter
Claims 16 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 6, 7, 12, 14, 15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, The image sensor according to claim 5, wherein each of the overflow modules comprises the overflow transistor and the overflow capacitor, and two or more overflow capacitors are coupled to the same node through corresponding transfer modules, wherein corresponding overflow capacitors are replaced by a shared overflow capacitor, and a second terminal of the corresponding overflow transistor is coupled to a third potential through the shared overflow capacitor; corresponding transfer modules are replaced by a shared transfer module, wherein the shared transfer module comprises a shared transistor, wherein a control terminal of the shared transistor receives a common shift control signal, wherein a first terminal of the shared transistor is coupled to a corresponding shared overflow capacitor, and a second terminal of the shared transistor is coupled to a corresponding node.
Regarding claim 7, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the image sensor according to claim 1, wherein each of the photosensitive modules comprises a transmission transistor and a photosensitive element, wherein a control terminal of the transmission transistor receives a transmission control signal, wherein a first terminal of the transmission transistor is coupled to the floating diffusion node, and a second terminal of the transmission transistor is coupled to a fourth potential through the photosensitive element and is coupled to a corresponding overflow module; and/or, the reset module comprises a reset transistor, wherein a control terminal of the reset transistor receives a reset control signal, wherein a first terminal the reset transistor is coupled to a fifth potential, and a second terminal of the reset transistor is coupled to the floating diffusion node; wherein each of the pixel units comprises the gain module, and the gain module is coupled between the reset module and the floating diffusion node, wherein the second terminal of the reset transistor is coupled to the gain module; and/or, the readout module comprises a source follower transistor and a selection transistor, wherein a control terminal of the source follower transistor is coupled to the floating diffusion node, wherein a first terminal of the source follower transistor is coupled to a sixth potential, and a second terminal of the source follower transistor is coupled to the first terminal of the selection transistor, wherein the control terminal receives a select control signal, and the second terminal is coupled to a column line.
Regarding claim 12, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the arrangement structure of the image sensor according to claim 11, wherein corresponding transfer modules are replaced by a shared transfer module, the shared transfer module comprises shared transfer transistor arranged at any of positions of replaced transfer transistor.
Regarding claim 14, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the arrangement structure of the image sensor according to claim 13, wherein each overflow transistor is arranged in the second corner area of the corresponding photosensitive element, wherein the reset module and the readout module are arranged in the second area; wherein each overflow transistor is arranged in the third corner area of the corresponding photosensitive element, the reset module and the readout module are arranged outside the first area relative to an edge or corner of the first corner area and the third corner area, wherein an arrangement direction of the reset module and the readout module is parallel to an arrangement direction of the first corner area and the third corner area.
Regarding claim 15, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the arrangement structure of the image sensor according to claim 8, wherein the reset module comprises a reset transistor, and the readout module comprises a source follower transistor and a selection transistor; the reset module and the readout module are arranged in the second area, wherein the floating diffusion node comprises a first node area and a second node area, wherein the first node area and the second node area are both symmetrically arranged between the corresponding transmission transistors, the source follower transistor is arranged between two node areas, the reset transistor is arranged outside any node area, and the selection transistor is arranged outside the source follower transistor remote from node areas; the reset module and the readout module are arranged outside the first area relative to an edge or corner of the first corner area and the third corner area, wherein the source follower transistor is arranged corresponding to the floating diffusion node, and the reset transistor and the selection transistor are arranged on both sides of the source follower transistor.
Regarding claim 18, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, a control method of the image sensor according to claim 1, comprising: a reset stage, during which a reset operation is performed on the floating diffusion node, the photosensitive modules, and the overflow modules; an exposure stage, during which the overflow modules are controlled to be turned on and the transfer modules are controlled to be turned off, wherein each of the photosensitive modules generates a first charge signal and a second charge signal based on photoelectric conversion, wherein the first charge signal is stored in each of the photosensitive modules, and the second charge signal is stored in each of the overflow modules; a readout stage, during which the overflow modules are controlled to be turned off, thereby performing a quantitative readout of the first reset signal and the first charge signal based on the floating diffusion node; quantizing the readout of the second reset signal based on the floating diffusion node, and then controlling the transfer modules to turned on, transferring the second charge signal to the floating diffusion node for quantitative readout; and/or, controlling the transfer modules to turn on, transferring the second charge signal to the floating diffusion node for quantization readout, and then performing a reset operation on the floating diffusion node for quantitative readout of the second reset signal.
Regarding claims 19 and 20, claims depend from claim 18, and are allowable for the same reasons stated above.
Conclusion
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/JOHN H MOREHEAD III/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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