Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive.
According to pages 6-7 of 11, Applicant's argument that
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, is not persuasive.
It is noted that Byun clearly teaches reading, by the controller (Fig. 1-4 and 11A; memory system 110 comprises a controller 130), update data for updating an operation of the storage memory from the storage memory after transferring the first line data ([0225-0226]; While in the sleep mode, the memory system 110 may supply power to a first volatile memory device therein, and suspend power to the second volatile memory VOLATILE MEMORY2. As a result, the second volatile memory VOLATILE MEMORY2 to which power is suspended during the sleep mode may lose all of the internal data INDATA stored therein, and the first volatile memory device to which power is supplied may retain the data stored therein. Thus, reads on “read and updating an operation of the storage memory” of memory system 110 after transferring the internal data INDATA to the host 102), and during processing of the transferred first line data by the processor (i.e. host 102 comprises processor 104) ([0226]; The host 102 may store the internal data INDATA received from the memory system 110 in the internal memory INTERNAL MEMORY of the host 102 during the time period when the memory system 110 is entering, in, and exiting the sleep mode.). Thus, Byun teaches the amended limitation for claim 1 and similar for amended limitation for claim 11.
According to pages 9-10 of 11, Applicant's argument that
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, is not persuasive.
In response to applicant's argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US 2014/0232731 hereinafter Holland) in view of Hong ( US 2005/0140619 hereinafter Hong), and Byun et al. (US 2020/0334166 hereinafter Byun).
Referring to claim 1, Holland discloses a method of driving a controller ([0016], Fig. 1; controller unit of system 100), comprising:
requesting, by a processor (Fig. 1; processor unit 108, display processing unit 110), first line data from a controller (Fig. 1; fabric 102) ([0025]; In various embodiments, memory 106 may be controlled by memory controller 104. Accordingly, memory controller 104 may facilitate the performance of read and write operations responsive to data requests received via fabric 102 from units 108 and 110.);
extracting, by the controller (Fig. 1; fabric 102) ([0020]; Accordingly, in some embodiments, fabric 102 may include one or more buses, controllers, interconnects, and/or bridges. In some embodiments, fabric 102 may implement a single communication protocol and elements coupled to fabric 102 may convert from the single communication protocol to other communication protocols internally.), the first line data from a storage memory and loading the extracted first line data into a shared memory (Fig. 1; memory 106) ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.);
transferring, by the controller (Fig. 1; fabric 102), the first line data loaded into the shared memory (Fig. 1; memory 106) to the processor (Fig. 1; processor unit 108, display processing unit 110) ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.).
However, Holland does not explicitly disclose a method of driving a timing controller, comprising: reading, by the controller, update data for updating an operation of the storage memory from the storage memory after transferring the first line data, and during processing of the transferred first line data by the processor.
In an analogous art, Hong discloses a method of driving a timing controller (Hong- [0042]; FIG. 5 is a detailed block diagram showing the timing controller of the driving apparatus shown in FIG. 4. As shown in FIG. 5, the timing controller 38 includes a gate control signal generator 50, a data control signal generator 52 and the encoding block 40. The gate control signal generator 50 generates the gate control signal GCS using the vertical/horizontal synchronizing signals V and H, the clock signal DCLK and the data enable signal DE. In particular, the gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Hong to the system of Holland in order to minimize the bit transition amount of the pixel data before applying to the data driver.
However, Holland in view of Hong does not explicitly disclose reading, by the controller, update data for updating an operation of the storage memory from the storage memory after transferring the first line data, and during processing of the transferred first line data by the processor.
In an analogous art, Byun discloses reading, by the controller (Fig. 1-4 and 11A; memory system 110 comprises a controller 130), update data for updating an operation of the storage memory from the storage memory after transferring the first line data ([0225-0226]; While in the sleep mode, the memory system 110 may supply power to a first volatile memory device therein, and suspend power to the second volatile memory VOLATILE MEMORY2. As a result, the second volatile memory VOLATILE MEMORY2 to which power is suspended during the sleep mode may lose all of the internal data INDATA stored therein, and the first volatile memory device to which power is supplied may retain the data stored therein. Thus, reads on “reading and updating an operation of the storage memory” of memory system 110 after transferring the internal data INDATA to the host 102)), and during processing of the transferred first line data by the processor (i.e. host 102 comprises processor 104) ([0226]; The host 102 may store the internal data INDATA received from the memory system 110 in the internal memory INTERNAL MEMORY of the host 102 during the time period when the memory system 110 is entering, in, and exiting the sleep mode.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Byun to the system of Holland in view of Hong in order to improve the data input and output performance of the memory system.
Referring to claim 2, Holland as modified by Byun discloses further comprising loading the update data read by the controller into the shared memory (Byun-[0312]; In this case, the controller 130 may not request one map data L2P, but may request a map segment as a plurality of map data L2P for a preset range of logical addresses including the corresponding logical address. Further, the memory device 150 may transmit the corresponding map segment to the controller 130. When specific map data L2P is updated, the controller 130 may update the map data L2P in the map segment loaded to the memory 144, and then program the updated map segment to the memory device 150 at a specific time point.).
Referring to claim 3, Holland as modified by Byun discloses wherein the loading includes loading the update data read by the controller into a reserved area of the shared memory (Byun- [0136]; As an amount of data which can be stored in the memory system 110 increases, an amount of metadata corresponding to the data stored in the memory system 110 also increases. When storage capability used to load the metadata in the memory 144 of the controller 130 is limited or restricted, the increase in an amount of loaded metadata may cause an operational burden on operations of the controller 130. For example, because of limitation of space or region allocated for metadata in the memory 144 of the controller 130, only a part of the metadata may be loaded.).
Referring to claim 4, Holland as modified by Byun discloses wherein the reserved area is a different area from an area in which the line data is loaded among storage areas of the shared memory (Byun- [0109]; the memory 144 may be implemented with a volatile memory. For example, the memory 144 may be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both. Thus, SRAM has reserved memory space…. and Fig. 20; memory 144 has a map cache 1441 and a map management data 1442 reads on “different storage areas”.).
Referring to claim 5, Holland as modified by Byun discloses wherein the shared memory (Fig. 20; memory 144) is included in the controller (Fig. 20; controller 130), and the storage memory (Fig. 20; memory 144) stores a plurality of pieces of region data including a plurality of pieces of line data (Byun- Fig. 20; memory 144 comprises a map cache 1441 that stores segments data read on “pieces of region data” and a map management data 1442 that stores MM/MISS tables read on “pieces of line of data”).
Referring to claim 6, Holland as modified by Byun discloses where the requesting includes:
transmitting, by the processor, a first request signal requesting the loading of the first line data, and a first address signal for the first line data to be loaded to the controller (Byun- [0053]; In an embodiment, a memory system can include a memory device configured to store a piece of data in a location which is distinguished by a physical address; and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system…, [0054]; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory, to calculate a map miss ratio based on a total read count and the map miss count and to determine the timing of transferring the piece of map data based on the map miss ratio…, and [0055]; The controller can be configured to select the piece of map data, which would be transferred, based on a read count corresponding to a map segment including the piece of map data.); and
receiving, by the controller, the first request signal and the first address signal (Byun- [0053]; In an embodiment, a memory system can include a memory device configured to store a piece of data in a location which is distinguished by a physical address; and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system.).
Referring to claim 7, Holland as modified by Byun discloses wherein the loading includes:
extracting, by the controller, the first line data corresponding to the first address signal from the storage memory in response to the first request signal (Byun- [0054; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory);
loading, by the controller, the extracted first line data into the shared memory (Byun- [0054; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory); and
transmitting, by the controller, a first completion signal to the processor upon completing
the loading of the extracted first line data ([0055]; The controller can be configured to select the piece of map data, which would be transferred, based on a read count corresponding to a map segment including the piece of map data).
Referring to claim 8, Holland as modified by Byun discloses wherein the reading includes reading, by the controller, the update data from the storage memory, and loading the read update data into the shared memory (Byun- [0053]; In an embodiment, a memory system can include a memory device configured to store a piece of data in a location which is distinguished by a physical address; and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system…, [0054]; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory, to calculate a map miss ratio based on a total read count and the map miss count and to determine the timing of transferring the piece of map data based on the map miss ratio…, and [0108]; The memory 144 may be a sort of working memory in the memory system 110 or the controller 130, while storing temporary or transactional data occurred or delivered for operations in the memory system 110 and the controller 130. For example, the memory 144 may temporarily store a piece of read data outputted from the memory device 150 in response to a request from the host 102, before the piece of read data is outputted to the host 102.).
Referring to claim 9, Holland as modified by Byun discloses further comprising:
after loading all the update data into the shared memory, receiving, by the controller, a
second request signal requesting loading of second line data and a second address signal for the second line data to be loaded from the processor;
extracting, by the controller, the second line data corresponding to the second address
signal from the storage memory in response to the second request signal;
loading, by the controller, the extracted second line data into the shared memory; and
upon completing the loading of the extracted second line data, transmitting, by the
controller, a second completion signal to the processor (Byun- [0092]; The host 102 may transmit a plurality of commands corresponding to the user's requests into the memory system 110, thereby performing operations corresponding to commands within the memory system 110…, [0108]; The memory 144 may be a sort of working memory in the memory system 110 or the controller 130, while storing temporary or transactional data occurred or delivered for operations in the memory system 110 and the controller 130. For example, the memory 144 may temporarily store a piece of read data outputted from the memory device 150 in response to a request from the host 102, before the piece of read data is outputted to the host 102…. and [0114]; When the memory device 150 includes a plurality of dies (or a plurality of chips) including non-volatile memory cells, the controller 130 may be configured to perform a parallel processing regarding plural requests or commands inputted from the host 102 in to improve performance of the memory system 110. For example, the transmitted requests or commands may be divided into and processed simultaneously in a plurality of dies or a plurality of chips in the memory device 150. Thus, the requests read on “receiving, by the controller, a
second request signal requesting loading of second line data and a second address signal for the second line data to be loaded from the processor” which performs the repeating steps of the first request.).
Referring to claim 11, Holland discloses a controller ([0016], Fig. 1; controller unit of system 100) comprising:
a storage memory (Fig. 1; storage 112) that stores a plurality of pieces of region data including a plurality of pieces of line data ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.);
a processor (Fig. 1; processor unit 108, display processing unit 110) that requests loading of the plurality of pieces of line data ([0025]; In various embodiments, memory 106 may be controlled by memory controller 104. Accordingly, memory controller 104 may facilitate the performance of read and write operations responsive to data requests received via fabric 102 from units 108 and 110. Memory controller 104 may perform various memory physical interface (PHY) functions such as memory refreshing, memory row-address and column-address strobe operations, etc. As discussed below, memory controller 104 may also be used to power-manage memory 106. The image data may be accessed via fabric 102 and transferred to display processing unit 110 as discussed further below.), receives and processes the loaded line data, and transmits the processed line data ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.); and
a controller (Fig. 1; fabric 102) that includes a shared memory (Fig. 1; memory 106), in which the line data is loaded and transmitted, and loads line data extracted from the storage memory (Fig. 1; storage 112) into the shared memory (Fig. 1; memory 106) in response to the request signal ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.),
wherein the controller (Fig. 1; fabric 102) is configured to:
transfer the line data loaded into the shared memory (Fig. 1; memory 106) to the processor (Fig. 1; processor unit 108, display processing unit 110) ([0026]; In various embodiments, storage device 112 may store program instructions (e.g., applications) executable by processor unit 108. In certain embodiments, storage device 112 may store a plurality of image data that may be transferred to memory 106 (i.e., so that future requests for that data can be served faster) or transferred to display processing unit 110 directly.).
However, Holland does not explicitly disclose a timing controller comprising:
a processor that requests loading of the plurality of pieces of line data included in the region data using a request signal and an address signal; and
read update data for updating an operation of the storage memory from the storage memory after transferring the line data, and during processing of the transferred first line data by the processor.
In an analogous art, Hong discloses a timing controller (Hong-[0042]; FIG. 5 is a detailed block diagram showing the timing controller of the driving apparatus shown in FIG. 4. As shown in FIG. 5, the timing controller 38 includes a gate control signal generator 50, a data control signal generator 52 and the encoding block 40. The gate control signal generator 50 generates the gate control signal GCS using the vertical/horizontal synchronizing signals V and H, the clock signal DCLK and the data enable signal DE. In particular, the gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Hong to the system of Holland in order to minimized the bit transition amount of the pixel data before applying to the data driver.
However, Holland does not explicitly disclose a processor that requests loading of the plurality of pieces of line data included in the region data using a request signal and an address signal; and
read update data for updating an operation of the storage memory from the storage memory after transferring the line data, and during processing of the transferred first line data by the processor.
In an analogous art, Byun discloses a processor that requests loading of the plurality of pieces of line data included in the region data using a request signal and an address signal (Byun-[0044]; When the external device may include the map information, the external device can transfer a request along with the logical address which the external device uses for indicating a piece of data and the physical address which the memory system independently uses but the external device does not use); and
(Fig. 1-4 and 11A; memory system 110 comprises a controller 130) read update data for updating an operation of the storage memory from the storage memory after transferring the line data ([0225-0226]; While in the sleep mode, the memory system 110 may supply power to a first volatile memory device therein, and suspend power to the second volatile memory VOLATILE MEMORY2. As a result, the second volatile memory VOLATILE MEMORY2 to which power is suspended during the sleep mode may lose all of the internal data INDATA stored therein, and the first volatile memory device to which power is supplied may retain the data stored therein. Thus, reads on “updating an operation of the storage memory” of memory system 110 after transferring the internal data INDATA to the host 102), and during processing of the transferred first line data by the processor (i.e. host 102 comprises processor 104) ([0226]; The host 102 may store the internal data INDATA received from the memory system 110 in the internal memory INTERNAL MEMORY of the host 102 during the time period when the memory system 110 is entering, in, and exiting the sleep mode.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Byun to the system of Holland in view of Hong in order to improve the data input and output performance of the memory system.
Referring to claim 12, Holland as modified by Byun discloses wherein the controller reads update data from the storage memory and loads the read update data into the shared memory while the processor is processing the line data (Byun-[0312]; In this case, the controller 130 may not request one map data L2P, but may request a map segment as a plurality of map data L2P for a preset range of logical addresses including the corresponding logical address. Further, the memory device 150 may transmit the corresponding map segment to the controller 130. When specific map data L2P is updated, the controller 130 may update the map data L2P in the map segment loaded to the memory 144, and then program the updated map segment to the memory device 150 at a specific time point.).
Referring to claim 13, Holland as modified by Byun discloses wherein the controller loads the read update data into a reserved area of the shared memory (Byun- [0136]; As an amount of data which can be stored in the memory system 110 increases, an amount of metadata corresponding to the data stored in the memory system 110 also increases. When storage capability used to load the metadata in the memory 144 of the controller 130 is limited or restricted, the increase in an amount of loaded metadata may cause an operational burden on operations of the controller 130. For example, because of limitation of space or region allocated for metadata in the memory 144 of the controller 130, only a part of the metadata may be loaded.).
Referring to claim 14, Holland as modified by Byun discloses wherein the reserved area is a different area from an area in which the line data is loaded among storage areas of the shared memory (Byun- [0109]; the memory 144 may be implemented with a volatile memory. For example, the memory 144 may be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both. Thus, SRAM has reserved memory space…. and Fig. 20; memory 144 has a map cache 1441 and a map management data 1442 reads on “different storage areas”.).
Referring to claim 15, Holland as modified by Byun discloses wherein the controller, upon receiving the request signal and the address signal from the processor, extracts the line data corresponding to the address signal from the storage memory in response to the request signal, and loads the extracted line data into the shared memory (Byun- [0053]; In an embodiment, a memory system can include a memory device configured to store a piece of data in a location which is distinguished by a physical address; and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system…. and [0054]; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory, to calculate a map miss ratio based on a total read count and the map miss count and to determine the timing of transferring the piece of map data based on the map miss ratio.).
Referring to claim 16, Holland as modified by Byun discloses wherein the controller reads the update data from the storage memory in response to the transfer of the line data, and loads the read update data into the shared memory (Byun- [0054; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory).
Referring to claim 17, Holland as modified by Byun discloses wherein the controller, when a request for next line data is received from the processor after loading all the update data into the shared memory, extracts the next line data from the storage memory, and stores the extracted next line data in the shared memory (Byun- [0053]; In an embodiment, a memory system can include a memory device configured to store a piece of data in a location which is distinguished by a physical address; and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system…, [0054]; By the way of example but not limitation, the controller can be configured to determine a map miss count based on whether the physical address associated with the logical address, which is inputted from the external device, is loaded in a cache memory, to calculate a map miss ratio based on a total read count and the map miss count and to determine the timing of transferring the piece of map data based on the map miss ratio…, and [0108]; The memory 144 may be a sort of working memory in the memory system 110 or the controller 130, while storing temporary or transactional data occurred or delivered for operations in the memory system 110 and the controller 130. For example, the memory 144 may temporarily store a piece of read data outputted from the memory device 150 in response to a request from the host 102, before the piece of read data is outputted to the host 102.).
Referring to claim 20, Holland as modified by Byun discloses wherein the update data has the same size as a size of one sector of the storage memory ([0210]; User data to be stored in the memory device 150 may be divided by the unit of a segment having a preset size. The preset size may be the same as a minimum data size required for the memory system 110 to interoperate with the host 102. According to an embodiment, a size of a data segment as the unit of user data may be determined according to a configuration and a control method in the memory device 150.).
Claims 10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US 2014/0232731 hereinafter Holland) in view of Hong ( US 2005/0140619 hereinafter Hong), Byun et al. (US 2020/0334166 hereinafter Byun), and Schober (US 6,976,142 hereinafter Schober).
Referring to claim 10, Holland as modified by Byun discloses wherein the reading further includes:
receiving, by the controller, a second request signal requesting loading of second line data and a second address signal for the second line data to be loaded from the processor while loading the update data into the shared memory;
upon loading all the update data into the shared memory, extracting, by the controller, the second line data corresponding to the second address signal from the storage memory in response to the second request signal;
loading, by the controller, the extracted second line data into the shared memory; and
upon completing the loading of the extracted second line data, transmitting, by the
controller, a second completion signal to the processor (Byun- [0092]; The host 102 may transmit a plurality of commands corresponding to the user's requests into the memory system 110, thereby performing operations corresponding to commands within the memory system 110…, [0108]; The memory 144 may be a sort of working memory in the memory system 110 or the controller 130, while storing temporary or transactional data occurred or delivered for operations in the memory system 110 and the controller 130. For example, the memory 144 may temporarily store a piece of read data outputted from the memory device 150 in response to a request from the host 102, before the piece of read data is outputted to the host 102…. and [0114]; When the memory device 150 includes a plurality of dies (or a plurality of chips) including non-volatile memory cells, the controller 130 may be configured to perform a parallel processing regarding plural requests or commands inputted from the host 102 in to improve performance of the memory system 110. For example, the transmitted requests or commands may be divided into and processed simultaneously in a plurality of dies or a plurality of chips in the memory device 150. Thus, the requests read on “receiving, by the controller, a second request signal requesting loading of second line data and a second address signal for the second line data to be loaded from the processor while loading the update data into the shared memory” which performs the repeating steps of the first request.).
However, Holland in view of Hong, and Byun as applied above does not explicitly disclose holding, by the controller, the second request signal and the second address signal.
In an analogous art, Schober discloses holding, by the controller, the second request signal and the second address signal (Schober- Col. 7 lines 36-49; For example, in situations where access to the same memory location is attempted within two clock cycles of a preceding read, the data may be stale. This results because while the second request is accessing the data, the previous request has already retrieved the data and may be modifying the data. Thus, the second request is not working with an accurate copy of the data. The typical method of preventing the retrieval of stale data (e.g., inaccurate data) is to hold the second request back until the first request has modified (e.g., via computations, etc.) and written the data back to memory. However, in the exemplary embodiment, as will be explained in FIG. 9 below, bypasses may be utilized to allow the access of data in consecutive clock cycles while at the same time assuring the accuracy of the data.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Schober to the system of Holland in view of Hong, and Byun in order to prevent the retrieval of stale data upon the second request.
Referring to claim 18, Holland in view of Hong, and Byun as applied above does not explicitly disclose wherein the controller, when a request for next line data is received from the processor while loading the update data into the shared memory, holds the request for the next line data.
In an analogous art, Schober discloses wherein the controller, when a request for next line data is received from the processor while loading the update data into the shared memory, holds the request for the next line data (Schober- Col. 7 lines 36-49; For example, in situations where access to the same memory location is attempted within two clock cycles of a preceding read, the data may be stale. This results because while the second request is accessing the data, the previous request has already retrieved the data and may be modifying the data. Thus, the second request is not working with an accurate copy of the data. The typical method of preventing the retrieval of stale data (e.g., inaccurate data) is to hold the second request back until the first request has modified (e.g., via computations, etc.) and written the data back to memory. However, in the exemplary embodiment, as will be explained in FIG. 9 below, bypasses may be utilized to allow the access of data in consecutive clock cycles while at the same time assuring the accuracy of the data.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Schober to the system of Holland in view of Hong, and Byun in order to prevent the retrieval of stale data upon the second request.
Referring to claim 19, Holland in view of Hong, and Byun as applied above does not explicitly disclose wherein the controller holds the request for the next line data during a time taken to load all the update data into the shared memory.
In an analogous art, Schober discloses wherein the controller holds the request for the next line data during a time taken to load all the update data into the shared memory (Schober- Col. 7 lines 36-49; For example, in situations where access to the same memory location is attempted within two clock cycles of a preceding read, the data may be stale. This results because while the second request is accessing the data, the previous request has already retrieved the data and may be modifying the data. Thus, the second request is not working with an accurate copy of the data. The typical method of preventing the retrieval of stale data (e.g., inaccurate data) is to hold the second request back until the first request has modified (e.g., via computations, etc.) and written the data back to memory. However, in the exemplary embodiment, as will be explained in FIG. 9 below, bypasses may be utilized to allow the access of data in consecutive clock cycles while at the same time assuring the accuracy of the data.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Schober to the system of Holland in view of Hong, and Byun in order to prevent the retrieval of stale data upon the second request.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT D AU whose telephone number is (571)272-5948. The examiner can normally be reached M-F. General 8am-5pm.
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/SCOTT D AU/ Examiner, Art Unit 2624
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