DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 10-13,16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Steward et al. (USP 7,026,975).
Regarding claim 1, Steward et al. discloses SAR ADC architecture that teaches: a digital-to-analog converter (DAC) configured to generate an analog output signal; a comparator including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and an array of switches coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 4 and its descriptions).
Regarding claim 2, Steward further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 4 and its descriptions).
Regarding claim 5, Steward further teaches: wherein the comparator is reset by a comparator reset clock, the array of switches not controlled by the comparator reset clock (see figure 4 and its descriptions).
Regarding claim 10, Steward further teaches: wherein the DAC is a capacitive DAC (see figure 4 and its descriptions).
Regarding claim 11, Steward further teaches: a sample and hold circuit (same as track and hold (T/H) circuit) configured to provide an analog input signal to a reference input of the DAC (see figure 4 and its descriptions).
Regarding claim 12, claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1 such as: Steward et al. discloses SAR ADC architecture that teaches: a digital-to-analog converter (DAC) configured to generate an analog output signal; a comparator including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and an array of switches coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 4 and its descriptions).
Regarding claim 13, claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2 such as: Steward further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 4 and its descriptions).
Regarding claim 16, claim 16 is similar to claim 5 in method format. Therefore, claim 16 is rejected as well as rejected in claim 5 such as: Steward further teaches: wherein the comparator is reset by a comparator reset clock, the array of switches not controlled by the comparator reset clock (see figure 4 and its descriptions).
Regarding claim 20, claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well as rejected in claim 10 such as: wherein the DAC is a capacitive DAC.
Claims 1-2, 12-13 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hurrell et al. (USP 10,333,543).
Regarding claims 1 and/or 12, Hurrell et al. discloses ADC architecture that teaches: a digital-to-analog converter (DAC)(102) configured to generate an analog output signal; a comparator (104) including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and an array of switches (112,114) coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 1 and its descriptions). Claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1.
Regarding claims 2 and/or 13, Hurrell further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 1 and its descriptions). Claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2.
Regarding claims 10 and/or 20, Hurrell further teaches: wherein DAC is a capacitive DAC. Claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well rejected in claim 10.
Claims 1-2, 12-13 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kapusta et al. (US 2012/0306671).
Regarding claims 1 and/or 12, Kapusta et al. discloses ADC architecture in figure 6 that teaches: a digital-to-analog converter (DAC)(610)) configured to generate an analog output signal; a comparator (615) including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and a logic (620) (logic circuit function as same as an array of switches ) coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 6 and its descriptions). Claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1.
Regarding claims 2 and/or 13, Kapusta further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 6 and its descriptions). Claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2.
Regarding claims 10 and/or 20, Kapusta further teaches: wherein DAC is a capacitive DAC (see figure 6 and its descriptions). Claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well rejected in claim 10.
Claims 1-2, 12-13 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martens et al. (USP 10,484,000).
Regarding claims 1 and/or 12, Martens et al. discloses ADC architecture in figure 6 that teaches: a digital-to-analog converter (DAC)(200a, 200b) configured to generate an analog output signal; a comparator (210) including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and a logic (240) (logic function as an array of switches) coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 6 and its descriptions). Claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1.
Regarding claims 2 and/or 13, Martens further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 6 and its descriptions). Claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2.
Regarding claims 10 and/or 20, Martens further teaches: wherein DAC is a capacitive DAC. Claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well rejected in claim 10.
Claims 1-2, 12-13 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shikata et al. (USP 10,454,492).
Regarding claims 1 and/or 12, Martens et al. discloses ADC architecture in figure 1 that teaches: a digital-to-analog converter (DAC)(102) configured to generate an analog output signal; a comparator (104) including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and a logic (106) (logic function as an array of switches) coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figure 1 and its descriptions). Claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1.
Regarding claims 2 and/or 13, further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figure 1 and its descriptions). Claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2.
Regarding claims 10 and/or 20, Martens further teaches: wherein DAC is a capacitive DAC. Claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well rejected in claim 10.
Claims 1-2, 12-13 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2023/0318616).
Regarding claims 1 and/or 12, Cheng. discloses SAR ADC architecture in figures 1 and 2 that teaches: a digital-to-analog converter (DAC) configured to generate an analog output signal; a comparator including an input configured to receive the analog output signal of the DAC and an output configured to generate a comparison signal; and a logic (logic function as an array of switches) coupled to the output of the comparator and configured to provide a feedback signal to a digital input of the DAC, wherein no latches are present along a signal path from the output of the comparator to the digital input of the DAC through the array of switches (see figures 1 and 2 and descriptions). Claim 12 is similar to claim 1 in method format. Therefore, claim 12 is rejected as well as rejected in claim 1.
Regarding claims 2 and/or 13, Cheng further teaches: wherein each switch of the array of switches includes an input configured to receive the comparison signal and an output, each switch controlled by a corresponding switch turn-off signal derived from the output of the switch (see figures 1 and 2 and descriptions). Claim 13 is similar to claim 2 in method format. Therefore, claim 13 is rejected as well as rejected in claim 2.
Regarding claims 10 and/or 20, Cheng further teaches: wherein DAC is a capacitive DAC (see figure 4). Claim 20 is similar to claim 10 in method format. Therefore, claim 20 is rejected as well rejected in claim 10.
Regarding claim 11, Cheng further teaches: a holding circuit configured to provide an analog input signal to a reference input of the DAC (see figures 1 and 2 and descriptions).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: an array of buffers each operable to buffer a corresponding switch of the array of switches.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: wherein the array of buffers directly drive the digital input of the DAC with no intervening components.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: wherein each switch of the array of switches is controlled by a local bit ready signal that is local to the switch.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: a bit ready detection circuit configured to generate the local bit ready signal based on detecting a signal transition of the switch.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: wherein the comparator comprises a pre-amp with a latch configured to receive the analog output signal of the DAC, and a comparator buffer coupled to an output of the preamp with the latch.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: wherein the comparator further comprises a timer coupled to an output of the comparator buffer with the latch and configured to generate a comparator reset clock that resets the preamp.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: providing buffering using an array of buffers each operable to buffer a corresponding switch of the array of switches.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: directly driving the digital input of the DAC using the array of buffers.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: controlling each switch of the array of switches by a local bit ready signal that is local to the switch.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: a bit ready detection circuit configured to generate the local bit ready signal based on detecting a signal transition of the switch.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features which is: wherein the comparator comprises a pre-amp with a latch configured to receive the analog output signal of the DAC and a comparator buffer coupled to an output of the preamp with the latch, the method further comprising using a timer coupled to an output of the comparator buffer and to generate a comparator reset clock that resets the preamp with the latch.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845
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