Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action is in response to the filing with the office dated 04/08/2025.
Claims 1, 11 AND 18 are independent claims. Claims 1-20 are presented in this office action.
Priority
3. Applicant’s claim for the benefit of a prior-filed Korean Patent Application No. 10-2024-0059917, filed on May 7, 2024 is acknowledged by the examiner.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/08/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
5. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite outputting shortest path and calculating betweenness centrality (BC) value.
Regarding claims 1, 11 AND 18 the limitations “calculating…” is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. that under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element precludes the steps from practically being performed by a human mentally or with pen and paper. These limitations, at the high level of generality as drafted, would encompass a user to calculate betweenness centrality (BC) value based on summing pair dependency values for respective pairs, which is mentally performable as an evaluation or judgement or with pen and paper. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, he claim recites the additional elements of, the invention being “electronic device”, “overhead hoist transport device”, “memory”
are recited at a high level of generality as generic computer components amount to nothing more than mere instructions to apply the recited abstract idea on a computer, under MPEP 2106.05(f). The additional element of output the shortest path is a data gathering step. Combination of these additional elements is no more than mere instructions to apply the exception using series of steps to perform the mental process Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. The “user selection” element that were identified as insignificant extra-solution activity as mere data outputting when re-evaluated still does not provide significantly more. Considering the additional elements in combination and the claim as a whole does not change the analysis, and does not amount to significantly more. Thus the claims are abstract.
The limitations identified as additional elements that are not sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the recitation of generic computing components is still mere instructions to apply the exception under MPEP 2106.05(f) and does not provide significantly more. The of “output shortest path” element that were identified as insignificant extra-solution activity as mere data gathering and outputting when re- evaluated still does not provide significantly more. Considering the additional elements in combination and the claim as a whole does not change the analysis, and does not amount to significantly more. Thus the claims are abstract.
Claims 2-10, 12-17, 19-20 recite further calculations which are based on the identified abstract idea of claim 1 are processes, that under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element precludes the steps from practically being performed by a human mentally or with pen and paper and likewise do not provide "significantly more" than the abstract idea for similar reasons as the independent claim. These limitations under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 3, 11, 12, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain; Ankur (US 20250286811 A1) in view of LEE; Min Joong (US 20130339290 A1).
Regarding independent claim 1, Jain; Ankur (US 20250286811 A1) teaches, an electronic device comprising: at least one memory configured to store at least one instruction; and at least one processor configured to execute the at least one instruction, wherein the at least one processor, by executing the at least one instruction, is configured to: output a first shortest path number, defined by a source node, a pass node, and a target node among a plurality of nodes to which a plurality of ports are connected; and a second shortest path number, defined by the source node and the target node, based on performing a shortest path calculation algorithm on the plurality of nodes and a plurality of links connecting the plurality of nodes (Paragraph [0066] discloses, output the k shortest path from source to destination with intermediated nodes in between the source and target node as Combining segments found from step (2) and step (3), the three k-shortest paths would be [0081] (i) A-B2-C2-Z (Cost=5), [0082] (ii) A-B1-C1-D1-Z (Cost=5), [0083] (iii) A-B1-C1-D2-Z (Cost=6));
a first port number defined as a number of ports connected to the source node among the plurality of ports, and a second port number defined as a number of ports connected to the target node among the plurality of ports (Paragraph [0016] The present disclosure will use the term port generally to refer to some hardware point where connectivity is realized. A computed path from a source node to a destination node will include a listing of ports from an ingress port on the source node to an egress port on the destination port, along with an ordered listing of all intermediate ports. Those skilled in the art will recognize Dijkstra's algorithm and Yen's algorithm can be used on the network graph 20 to k-shortest paths between nodes, at the port level).
Jain et al fails to explicitly teach, and calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, and wherein a first pair-dependency value is defined as a product of a second pair- dependency value defined as a ratio of the first shortest path number to the second shortest path number
LEE; Min Joong (US 20130339290 A1) teaches, and calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, and wherein a first pair-dependency value is defined as a product of a second pair- dependency value defined as a ratio of the first shortest path number to the second shortest path number, (Paragraphs [0100]-[0105] discloses, calculating betweenness centrality (BC) value based on the summing the ratio of all pair vertices computing the shortest path. Also see [0013]),
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al by calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, and wherein a first pair-dependency value is defined as a product of a second pair- dependency value defined as a ratio of the first shortest path number to the second shortest path number as taught by LEE; et al (Paragraph [0100]-[0105]).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, improves the computation time of the betweenness centrality based on a modified breadth-first search algorithm and the dependency of a vertex, and it is the fastest known algorithm that computes the exact betweenness centralities of all the vertices in a graph as taught by LEE et al (Paragraph [0006]).
Regarding dependent claim 3, Jain et al and LEE et al teach, the electronic device of claim 1.
Jain et al further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: determine whether there is port data on the plurality of ports; when there is no port data on the plurality of ports (Paragraph [0050] discloses, vertex C1 is discarded based on determining that there is no port data passing from C1- destination Z);
LEE et al further teaches, and calculate a second BC value for the plurality of nodes based on summing second pair-dependency values for the respective pairs of the source node and the target node among the plurality of nodes (Paragraph [0013] betweenness centrality was determined by first computing the lengths and number of shortest paths between all pairs, and then summing up pair-dependencies of all pairs).
Regarding independent claim 11, Jain; Ankur (US 20250286811 A1) teaches, a method of operating an electronic device, the method comprising: outputting a first shortest path number defined as a source node, a pass node, and a target node, among a plurality of nodes to which a plurality of ports are connected, and a second shortest path number defined based on the source node and the target node, based on performing a shortest path calculation algorithm on the plurality of nodes and a plurality of links connecting the plurality of nodes (Paragraph [0066] discloses, output the k shortest path from source to destination with intermediated nodes in between the source and target node as Combining segments found from step (2) and step (3), the three k-shortest paths would be [0081] (i) A-B2-C2-Z (Cost=5), [0082] (ii) A-B1-C1-D1-Z (Cost=5), [0083] (iii) A-B1-C1-D2-Z (Cost=6));
a first port number defined as a number of ports connected to the source node among the plurality of ports, and a second port number defined as a number of ports connected to the target node among the plurality of ports (Paragraph [0016] The present disclosure will use the term port generally to refer to some hardware point where connectivity is realized. A computed path from a source node to a destination node will include a listing of ports from an ingress port on the source node to an egress port on the destination port, along with an ordered listing of all intermediate ports. Those skilled in the art will recognize Dijkstra's algorithm and Yen's algorithm can be used on the network graph 20 to k-shortest paths between nodes, at the port level).
Jain et al fails to explicitly teach, and calculating a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, a first pair-dependency value being defined as a product of a second pair-dependency value defined as a ratio of the first shortest path number to the second shortest path number.
LEE; Min Joong (US 20130339290 A1) teaches, and calculating a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, a first pair-dependency value being defined as a product of a second pair-dependency value defined as a ratio of the first shortest path number to the second shortest path number (Paragraphs [0100]-[0105] discloses, calculating betweenness centrality (BC) value based on the summing the ratio of all pair vertices computing the shortest path. Also see [0013]),
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al by calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, and wherein a first pair-dependency value is defined as a product of a second pair- dependency value defined as a ratio of the first shortest path number to the second shortest path number as taught by LEE; et al (Paragraph [0100]-[0105]).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, improves the computation time of the betweenness centrality based on a modified breadth-first search algorithm and the dependency of a vertex, and it is the fastest known algorithm that computes the exact betweenness centralities of all the vertices in a graph as taught by LEE et al (Paragraph [0006]).
Regarding dependent claim 12, Jain et al and LEE et al teach, the method of claim 11.
Jain et al further teaches, further comprising: determining whether there is port data on the plurality of ports; when there is no port data on the plurality of ports (Paragraph [0050] discloses, vertex C1 is discarded based on determining that there is no port data passing from C1- destination Z);
LEE et al further teaches, and calculating a second BC value for the plurality of nodes based on summing second pair- dependency values for the respective pairs of the source node and the target node among the plurality of nodes (Paragraph [0013] betweenness centrality was determined by first computing the lengths and number of shortest paths between all pairs, and then summing up pair-dependencies of all pairs).
Regarding independent claim 18, Jain; Ankur (US 20250286811 A1) teaches, an electronic device comprising: a shortest path calculation circuit configured to output a first shortest path number defined as a source node, a pass node, and a target node, among a plurality of nodes to which a plurality of ports are connected, and a second shortest path number defined based on the source node and the target node, based on performing a shortest path calculation algorithm on the plurality of nodes and a plurality of links connecting the plurality of nodes (Paragraph [0066] discloses, output the k shortest path from source to destination with intermediated nodes in between the source and target node as Combining segments found from step (2) and step (3), the three k-shortest paths would be [0081] (i) A-B2-C2-Z (Cost=5), [0082] (ii) A-B1-C1-D1-Z (Cost=5), [0083] (iii) A-B1-C1-D2-Z (Cost=6));
a first port number defined as a number of ports connected to the source node among the plurality of ports, and a second port number defined as a number of ports connected to the target node among the plurality of ports (Paragraph [0016] The present disclosure will use the term port generally to refer to some hardware point where connectivity is realized. A computed path from a source node to a destination node will include a listing of ports from an ingress port on the source node to an egress port on the destination port, along with an ordered listing of all intermediate ports. Those skilled in the art will recognize Dijkstra's algorithm and Yen's algorithm can be used on the network graph 20 to k-shortest paths between nodes, at the port level).
Jain et al fails to explicitly teach, and a BC calculation circuit configured to calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, a first pair- dependency value being defined as a product of a second pair-dependency value defined as a ratio of the first shortest path number to the second shortest path number.
LEE; Min Joong (US 20130339290 A1) teaches, and a BC calculation circuit configured to calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, a first pair- dependency value being defined as a product of a second pair-dependency value defined as a ratio of the first shortest path number to the second shortest path number (Paragraphs [0100]-[0105] discloses, calculating betweenness centrality (BC) value based on the summing the ratio of all pair vertices computing the shortest path. Also see [0013]),
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al by calculate a first betweenness centrality (BC) value for the plurality of nodes based on summing first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes, and wherein a first pair-dependency value is defined as a product of a second pair- dependency value defined as a ratio of the first shortest path number to the second shortest path number as taught by LEE; et al (Paragraph [0100]-[0105]).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, improves the computation time of the betweenness centrality based on a modified breadth-first search algorithm and the dependency of a vertex, and it is the fastest known algorithm that computes the exact betweenness centralities of all the vertices in a graph as taught by LEE et al (Paragraph [0006]).
Regarding dependent claim 19, Jain et al and LEE et al teach, the electronic device of claim 18.
LEE et al further teaches, further comprising: a mode controller configured to select either one of a first mode, in which a second BC value is calculated based on node data on the plurality of nodes and link data on the plurality of links, and a second mode, in which the first BC value is calculated based on the node data, the link data, and port data on the plurality of ports (figs1, 2 Paragraphs [0080], [0084 discloses, loading from the memory/ prestored data graph data including calculated betweenness centrality value plurality of nodes and link data. Port data is taught by Jain et al Paragraph [0016]).
7. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jain; Ankur (US 20250286811 A1) in view of LEE; Min Joong (US 20130339290 A1) and in further view of OH; Chang Suk (US 20250218839 A1).
Regarding dependent claim 2, Jain et al and LEE et al teach, the electronic device of claim 1.
Jain et al and LEE et al fails to explicitly teach, wherein each of the plurality of nodes includes a sensor configured to sense an overhead hoist transport (OHT) device, and wherein each of the plurality of ports is configured to accommodate a container transported through the OHT device.
OH; Chang Suk (US 20250218839 A1) teaches, wherein each of the plurality of nodes includes a sensor configured to sense an overhead hoist transport (OHT) device, and wherein each of the plurality of ports is configured to accommodate a container transported through the OHT device (Paragraphs [0055], [0060] discloses, each of the nodes include sensor that detects the container is loaded, where the container is moved along the rail by an OHT vehicle).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by providing wherein each of the plurality of nodes includes a sensor configured to sense an overhead hoist transport (OHT) device, and wherein each of the plurality of ports is configured to accommodate a container transported through the OHT device, as taught by OH et al (Paragraphs [0055], [0060]).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, would optimize a container transfer operation between a container loading unit and a load port, and a substrate processing apparatus including the same.
8. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jain; Ankur (US 20250286811 A1) in view of LEE; Min Joong (US 20130339290 A1) and in further view of HU; Bo (US 20150256442 A1).
Regarding dependent claim 4, Jain et al and LEE et al teach, the electronic device of claim 1.
Jain et al and LEE et al fails to explicitly teach, wherein the at least one processor, by executing the at least one instruction, is further configured to calculate, in parallel, the first BC value for each of a plurality of node groups, each node group being formed by grouping the plurality of nodes.
HU; Bo (US 20150256442 A1) teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to calculate, in parallel, the first BC value for each of a plurality of node groups, each node group being formed by grouping the plurality of nodes (Paragraphs [0027]-[0029] discloses, calculating betweenness centrality measure in parallel for each region (Examiner interprets each node group as each region)).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by providing wherein the at least one processor, by executing the at least one instruction, is further configured to calculate, in parallel, the first BC value for each of a plurality of node groups, each node group being formed by grouping the plurality of nodes, as taught by HU et al (Paragraphs [0027]-[0029]).
One of the ordinary skill in the art would have been motivated to make this modification, by parallelizing some of the computation, the overall system bottleneck caused by the method is reduced or mitigated as taught by HU et al (Paragraph [0013].
9. Claims 5-7, 10, 13-15, 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jain; Ankur (US 20250286811 A1) in view of LEE; Min Joong (US 20130339290 A1) and in further view of lrik Brandes (Published in Journal of Mathematical Sociology 25(2):163-177, (2001)) hereby referred as Brandes.
Regarding dependent claim 5, Jain et al and LEE et al teach, the electronic device of claim 1.
Jain et al further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: output a sum port number for remaining nodes except for the source node among the plurality of nodes (Paragraph [0016] The present disclosure will use the term port generally to refer to some hardware point where connectivity is realized. A computed path from a source node to a destination node will include a listing of ports from an ingress port on the source node to an egress port on the destination port, along with an ordered listing of all intermediate ports. Those skilled in the art will recognize Dijkstra's algorithm and Yen's algorithm can be used on the network graph 20 to k-shortest paths between nodes, at the port level).
Jain et al and LEE et al fails to explicitly teach, cumulatively summing a third port number defined as a number of ports connected to the remaining node; and calculate a third BC value for the source node, based on cumulatively summing a product of the sum port number and the first port number for the source node.
Brandes teaches, teaches, based on cumulatively summing a third port number defined as a number of ports connected to the remaining node; and calculate a third BC value for the source node, based on cumulatively summing a product of the sum port number and the first port number for the source node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node (based on specification [0038] first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes by accumulating a BC value from a farthest node to the source node along predecessor nodes. Examiner interprets calculating an accumulation coefficient for a successor node is based on the pair dependency value. Examiner interprets cumulatively summing accumulation coefficient as a running total or cumulative sum which requires summing current values with all previous values. Also see Page 2 last two paragraphs) Nodes are taught by Jain et al (paragraph [0016]).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node, as taught by Brandes (Page 9).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, would reduce the combined time and space spent on computing different measures as taught by Brandes (Page 9).
Regarding dependent claim 6, Jain et al and LEE et al teach, the electronic device of claim 1.
Jain et al further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: output a sequence set defined as a node sequence for the target node from the source node based on performing the shortest path calculation algorithm (Paragraph [0051] discloses, output a sequence set defined by node sequence from source to target node based on shortest path such as A-B1-B2-B3-C2-Z, A-B1-B2-B3-B4-C3-Z);
Jain et al and LEE et al fails to explicitly teach, calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node.
Brandes teaches, calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node (based on specification [0038] first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes by accumulating a BC value. Examiner interprets calculating an accumulation coefficient for a successor node is based on the accumulating dependencies. Examiner interprets cumulatively summing accumulation coefficient as a running total or cumulative sum which requires summing current values/ iteration with all previous values/ iterations in sequence. Also see Page 2 last two paragraphs).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node, as taught by Brandes (Page 9).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, would reduce the combined time and space spent on computing different measures as taught by Brandes (Page 9).
Regarding dependent claim 7, Jain et al, LEE et al and Brandes teach, the electronic device of claim 6.
Brandes further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: update the first pair-dependency value based on cumulatively summing the accumulation coefficient for the one or more predecessor nodes for the successor node; determine whether the successor node is the source node; calculate a sum of the updated first pair-dependency value and a sum of the first port number and the second port number when the successor node is not the source node; and calculate the first BC value based on accumulating the sum while changing the successor node in a direction toward the source node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node) port numbers are taught by Jain et al (Paragraph [0016]);
Regarding dependent claim 10, Jain et al, LEE et al and Brandes teach, the electronic device of claim 6.
Brandes further teaches, wherein the accumulation coefficient is defined based on the first pair-dependency value, a product of the first port number and the second port number, and the first shortest path number (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node) port numbers are taught by Jain et al (Paragraph [0016]).
Regarding dependent claim 13, Jain et al and LEE et al teach, the method of claim 11.
Jain et al further teaches, further comprising: outputting a sum port number for remaining nodes except for the source node among the plurality of nodes (Paragraph [0016] The present disclosure will use the term port generally to refer to some hardware point where connectivity is realized. A computed path from a source node to a destination node will include a listing of ports from an ingress port on the source node to an egress port on the destination port, along with an ordered listing of all intermediate ports. Those skilled in the art will recognize Dijkstra's algorithm and Yen's algorithm can be used on the network graph 20 to k-shortest paths between nodes, at the port level).
Jain et al and LEE et al fails to explicitly teach, based on cumulatively summing a third port number defined as a number of ports connected to the remaining nodes; and calculating a third BC value for the source node based on cumulatively summing a product of the sum port number and the first port number for the source node.
Brandes teaches, teaches, based on cumulatively summing a third port number defined as a number of ports connected to the remaining nodes; and calculating a third BC value for the source node based on cumulatively summing a product of the sum port number and the first port number for the source node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node (based on specification [0038] first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes by accumulating a BC value from a farthest node to the source node along predecessor nodes. Examiner interprets calculating an accumulation coefficient for a successor node is based on the pair dependency value. Examiner interprets cumulatively summing accumulation coefficient as a running total or cumulative sum which requires summing current values with all previous values. Also see Page 2 last two paragraphs) Nodes are taught by Jain et al (paragraph [0016]).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node, as taught by Brandes (Page 9).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, would reduce the combined time and space spent on computing different measures as taught by Brandes (Page 9).
Regarding dependent claim 14, Jain et al and LEE et al teach, the method of claim 11.
Jain et al further teaches, further comprising: outputting a sequence set defined as a node sequence for the target node from the source node, based on performing the shortest path calculation algorithm (Paragraph [0051] discloses, output a sequence set defined by node sequence from source to target node based on shortest path such as A-B1-B2-B3-C2-Z, A-B1-B2-B3-B4-C3-Z);
Jain et al and LEE et al fails to explicitly teach, calculating an accumulation coefficient for a successor node included in the sequence set; and calculating a fourth BC value for the plurality of links based on cumulatively summing the accumulation coefficient for one or more predecessor nodes for the successor node.
Brandes teaches, calculating an accumulation coefficient for a successor node included in the sequence set; and calculating a fourth BC value for the plurality of links based on cumulatively summing the accumulation coefficient for one or more predecessor nodes for the successor node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node (based on specification [0038] first pair-dependency values for respective pairs of the source node and the target node among the plurality of nodes by accumulating a BC value. Examiner interprets calculating an accumulation coefficient for a successor node is based on the accumulating dependencies. Examiner interprets cumulatively summing accumulation coefficient as a running total or cumulative sum which requires summing current values/ iteration with all previous values/ iterations in sequence. Also see Page 2 last two paragraphs).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by calculate an accumulation coefficient for a successor node included in the sequence set; and calculate a fourth BC value for the plurality of links based on cumulatively summing accumulation coefficients for one or more predecessor nodes with respect to the successor node, as taught by Brandes (Page 9).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, would reduce the combined time and space spent on computing different measures as taught by Brandes (Page 9).
Regarding dependent claim 15, Jain et al, LEE et al and Brandes teach, the method of claim 14.
Brandes further teaches, further comprising: updating the first pair-dependency value based on accumulating the accumulation coefficient for the one or more predecessor nodes for the successor node; determining whether the successor node is the source node; calculating a sum of the updated first pair-dependency value and a product of the first port number and the second port number when the successor node is not the source node; and calculating the first BC value based on accumulating the sum while changing the successor node in a direction toward the source node (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node) port numbers are taught by Jain et al (Paragraph [0016]).
Regarding dependent claim 17, Jain et al, LEE et al and Brandes teach, the method of claim 14.
Brandes further teaches, wherein the accumulation coefficient is defined based on the first pair-dependency value, a product of the first port number and the second port number, and the first shortest path number (page 9 proof: discloses, calculating an accumulation coefficient for each vertex and calculating the betweenness centrality value at the end of each iteration, the dependencies of the source on each other vertex are added to the centrality score of that vertex which is cumulatively summing the values from predecessor nodes with respect to successor node) port numbers are taught by Jain et al (Paragraph [0016]).
10. Claims 8, 9, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jain; Ankur (US 20250286811 A1) in view of LEE; Min Joong (US 20130339290 A1) and in further view of Tressler; Eric P(US 9892533 B1).
Regarding dependent claim 8, Jain et al and LEE et al teach, the electronic device of claim 1.
LEE et al further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: load, from the at least one memory, at least two of node data on the plurality of nodes, link data on the plurality of links, and port data on the plurality of ports; select either one of a first mode, in which a second BC value is calculated based on the node data and the link data, and a second mode, in which the first BC value is calculated based on the node data, the link data, and the port data (figs1, 2 Paragraphs [0080], [0084 discloses, loading from the memory/ prestored data graph data including calculated betweenness centrality value plurality of nodes and link data. Port data is taught by Jain et al Paragraph [0016]).
Jain et al and LEE et al fails to explicitly teach, and control to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data.
Tressler; Eric P(US 9892533 B1) teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: load, from the at least one memory, at least two of node data on the plurality of nodes, link data on the plurality of links, and port data on the plurality of ports; select either one of a first mode, in which a second BC value is calculated based on the node data and the link data, and a second mode, in which the first BC value is calculated based on the node data, the link data, and the port data; and control to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data (Paragraph (10) The present invention is directed to a system, method, and computer program product for graph visualization. In various embodiments, the system includes one or more processors and a memory. The memory has executable instructions encoded on a non-transitory computer readable medium, such that upon execution of the instructions, the one or more processors perform several operations, such as receiving as an input a graph G=(V,E), where V is a set of vertices and E is a set of edges between the vertices; distributing vertices through a unit square; arranging the vertices to generate a graph layout, where arrangement of the vertices reflects a betweenness centrality; and displaying the graph layout on a display. Also see Summary).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by providing control to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data, as taught by Tressler et al (Paragraph (10)).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, the visualization technique addresses a wide range of general graph/network-based problems through exploratory analysis by a human observer, as taught by Tressler et al (Paragraph (49)).
Regarding dependent claim 9, Jain et al, LEE et al and Tressler et al teach, the electronic device of claim 8.
LEE et al further teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: load the node data and the link data from the at least one memory based on the first mode being selected; and load the node data, the link data, and the port data from the at least one memory based on the second mode being selected (figs1, 2 Paragraphs [0080], [0084 discloses, loading from the memory/ prestored data graph data including calculated betweenness centrality value plurality of nodes and link data. Port data is taught by Jain et al Paragraph [0016]).
Tressler et al also teaches, wherein the at least one processor, by executing the at least one instruction, is further configured to: load the node data and the link data from the at least one memory based on the first mode being selected; and load the node data, the link data, and the port data from the at least one memory based on the second mode being selected (Paragraph (10) The present invention is directed to a system, method, and computer program product for graph visualization. In various embodiments, the system includes one or more processors and a memory. The memory has executable instructions encoded on a non-transitory computer readable medium, such that upon execution of the instructions, the one or more processors perform several operations, such as receiving as an input a graph G=(V,E), where V is a set of vertices and E is a set of edges between the vertices; distributing vertices through a unit square; arranging the vertices to generate a graph layout, where arrangement of the vertices reflects a betweenness centrality; and displaying the graph layout on a display. Also see Summary).
Regarding dependent claim 16, Jain et al and LEE et al teach, the method of claim 11.
LEE et al further teaches, further comprising: loading at least two of node data on the plurality of nodes, link data on the plurality of links, and port data on the plurality of ports; selecting either one of a first mode for calculating a second BC value based on the node data and the link data and a second mode for calculating the first BC value based on the node data, the link data, and the port data (figs1, 2 Paragraphs [0080], [0084 discloses, loading from the memory/ prestored data graph data including calculated betweenness centrality value plurality of nodes and link data. Port data is taught by Jain et al Paragraph [0016]).
Jain et al and LEE et al fails to explicitly teach, and controlling to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data.
Tressler; Eric P(US 9892533 B1) teaches, further comprising: loading at least two of node data on the plurality of nodes, link data on the plurality of links, and port data on the plurality of ports; selecting either one of a first mode for calculating a second BC value based on the node data and the link data and a second mode for calculating the first BC value based on the node data, the link data, and the port data; and controlling to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data (Paragraph (10) The present invention is directed to a system, method, and computer program product for graph visualization. In various embodiments, the system includes one or more processors and a memory. The memory has executable instructions encoded on a non-transitory computer readable medium, such that upon execution of the instructions, the one or more processors perform several operations, such as receiving as an input a graph G=(V,E), where V is a set of vertices and E is a set of edges between the vertices; distributing vertices through a unit square; arranging the vertices to generate a graph layout, where arrangement of the vertices reflects a betweenness centrality; and displaying the graph layout on a display. Also see Summary).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by providing control to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data, as taught by Tressler et al (Paragraph (10)).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, the visualization technique addresses a wide range of general graph/network-based problems through exploratory analysis by a human observer, as taught by Tressler et al (Paragraph (49)).
Regarding dependent claim 20, Jain et al and LEE et al teach, the electronic device of claim 19.
Jain et al and LEE et al fails to explicitly teach, further comprising: a visualization circuit configured to visualize the first BC value or the second BC value to output visualization data for the plurality of nodes and the plurality of links.
Tressler; Eric P(US 9892533 B1) teaches, further comprising: a visualization circuit configured to visualize the first BC value or the second BC value to output visualization data for the plurality of nodes and the plurality of links (Paragraph (10) The present invention is directed to a system, method, and computer program product for graph visualization. In various embodiments, the system includes one or more processors and a memory. The memory has executable instructions encoded on a non-transitory computer readable medium, such that upon execution of the instructions, the one or more processors perform several operations, such as receiving as an input a graph G=(V,E), where V is a set of vertices and E is a set of edges between the vertices; distributing vertices through a unit square; arranging the vertices to generate a graph layout, where arrangement of the vertices reflects a betweenness centrality; and displaying the graph layout on a display. Also see Summary).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Jain et al and LEE et al by providing control to visualize the first BC value or the second BC value for the plurality of nodes and the plurality of links to output visualization data, as taught by Tressler et al (Paragraph (10)).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, the visualization technique addresses a wide range of general graph/network-based problems through exploratory analysis by a human observer, as taught by Tressler et al (Paragraph (49)).
Closest Prior Art
11. The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure.
Jain; Ankur (US 20220231938 A1) teaches, Systems and methods include, responsive to defining a routing graph that includes vertices for each node of a plurality of nodes in a network and edges for links interconnecting the plurality of nodes, receiving a request for k shortest paths, where k is an integer>0, between a source node and a destination node of the plurality of nodes; and determining the k shortest paths utilizing a k-shortest path algorithm that utilizes two threads in parallel for each shortest path query, wherein the two threads include i) a shortest path query from the source node to the destination node and ii) a shortest path query from the destination node to the source node. The determining further includes, responsive to a first thread in each shortest path query obtaining a result, utilizing the result from the first thread and terminating a second thread (Abstract).
12. Examiner has pointed out particular references contained in the prior arts of record in the body of this action for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and Figures may apply as well. It is respectfully requested from the applicant, in preparing the response, to consider fully the entire references as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior arts or disclosed by the examiner. It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968))).
Conclusion
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/S. R./
Examiner, Art Unit 2163
/ALEX GOFMAN/Primary Examiner, Art Unit 2163
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