DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2020/0303444 A1 to Onuki et al.
With respect to claim 1 Onuki discloses, in Fig. 1A-16C, a photoelectric conversion apparatus (abstract) comprising: a first substrate (300) having a pixel array (paragraph 109 and Fig. 1B); a second substrate (200) having a memory array configured to retain an analog signal output by the pixel array (paragraph 84 and Fig. 1B); and a third substrate (100) having an analog-to-digital conversion circuit configured to convert the analog signal output by the memory array into a digital signal (paragraph 74 and 115), the second substrate having at least one memory control circuit (221 and 222) configured to control the memory array (paragraph 85-86), and the first substrate or the third substrate having at least one pixel control circuit configured to control the pixel array (paragraph 112, 118 and/or paragraph 74 and 107; where both substrates have control circuits for the pixel array).
With respect to claim 2 Onuki discloses, in Fig. 1A-16C, a photoelectric conversion apparatus (abstract) comprising: a first substrate (300) having a pixel array (paragraph 109 and Fig. 1B); a second substrate (200) having a memory array configured to retain an analog signal output by the pixel array (paragraph 84 and Fig. 1B); and a third substrate (100) having an analog-to-digital conversion circuit configured to convert the analog signal output by the memory array into a digital signal (paragraph 74 and 115); at least one memory control circuit (221 and 222) configured to control the memory array (paragraph 85-86); and at least one pixel control circuit configured to control the pixel array (paragraph 74, 107, 112 and 118; where a plurality of circuits are provided to control the pixel array), at least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, or a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit, being electrically separated (paragraph 78; where power supply circuit 116 is provided on substrate 100 which satisfies the claim are it must be connected to the components either via the same node or electrically separated nodes).
With respect to claim 3 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein at least one of a power supply voltage node electrically connected to the pixel control circuit and a power supply voltage node electrically connected to the memory control circuit, or a reference voltage node electrically connected to the pixel control circuit and a reference voltage node electrically connected to the memory control circuit, is electrically separated (paragraph 78; where power supply circuit 116 is provided on substrate 100 which satisfies the claim are it must be connected to the components either via the same node or electrically separated nodes).
With respect to claim 4 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the pixel control circuit includes a pixel output circuit configured to output a control signal for controlling the pixel array (paragraph 112), and the memory control circuit includes a memory output circuit configured to output a control signal for controlling the memory array (paragraph 85).
With respect to claim 5 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein a pixel (312) included in the pixel array has a photoelectric conversion element (313) configured to generate charge in response to incident light, a floating diffusion (331) configured to convert the charge into a signal, and an amplification transistor (316) configured to amplify the signal, and the analog signal output by the pixel array is a signal output by the amplification transistor (Fig. 2D and paragraph 110 and corresponding Fig. 2D text starting at paragraph 120).
With respect to claim 6 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 5, wherein the analog signal output by the pixel array is a signal output by a source follower circuit including a current source and the amplification transistor, the current source being configured to supply current to the amplification transistor (Fig. 2D and paragraph 60-63 and 124-125; where for a current to flow through the transistor when operated there must be a connected current source).
With respect to claim 7 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the pixel array has a plurality of pixels disposed in a plurality of rows and a plurality of columns, the memory array has a plurality of memory circuits disposed in a plurality of rows and a plurality of columns, and each of the plurality of memory circuits is configured to retain the analog signal output from a corresponding one of the plurality of pixels (Fig. 1B and paragraph 84).
With respect to claim 8 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 7, wherein the pixel control circuit controls at least one pixel among the plurality of pixels to output the analog signal to the memory array, and the memory control circuit controls at least one memory circuit among the plurality of memory circuits to output the analog signal to the analog-to- digital conversion circuit (paragraph 84 and 264).
With respect to claim 9 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 7, wherein: the third substrate has a control circuit configured to control the pixel control circuit and the memory control circuit (paragraph 71); the plurality of pixels include a first pixel disposed in a first pixel row and a second pixel disposed in a second pixel row; the plurality of memory circuits include a first memory circuit disposed in a first memory row and a second memory circuit disposed in a second memory row; the control circuit controls the pixel control circuit such that, during a single frame, a first period during which the first pixel outputs the analog signal to the first memory circuit overlaps at least partially with a second period during which the second pixel outputs the analog signal to the second memory circuit; and the control circuit controls the memory control circuit such that, during the single frame, the first memory circuit and the second memory circuit sequentially output the analog signal to the analog-to-digital conversion circuit (the remainder of the claim is related to a manner of operating the sensor, as Onuki teaches all of the structures, as already discussed prior, Onuki anticipates the claims as the manner of operating the device does not differentiate it over the prior art if all of the structure is discloses – See MPEP 2114).
With respect to claim 10 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 9, wherein: the plurality of pixels include a third pixel disposed in a third pixel row and a fourth pixel disposed in a fourth pixel row; the plurality of memory circuits include a third memory circuit disposed in a third memory row and a fourth memory circuit disposed in a fourth memory row; the control circuit controls the pixel control circuit such that, during the single frame, a third period during which the third pixel outputs the analog signal to the third memory circuit overlaps at least partially with a fourth period during which the fourth pixel outputs the analog signal to the fourth memory circuit; the control circuit controls the memory control circuit such that, during the single frame, the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signal to the analog-to-digital conversion circuit; and the first period overlaps at least partially with the third period (the claim is related to a manner of operating the sensor, as Onuki teaches all of the structures, as already discussed prior, Onuki anticipates the claims as the manner of operating the device does not differentiate it over the prior art if all of the structure is discloses – See MPEP 2114).
With respect to claim 11 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 9, wherein: the plurality of pixels include a third pixel disposed in a third pixel row and a fourth pixel disposed in a fourth pixel row; the plurality of memory circuits include a third memory circuit disposed in a third memory row and a fourth memory circuit disposed in a fourth memory row; the control circuit controls the pixel control circuit and the memory control circuit such that, during the single frame, a third period during which the third pixel outputs the analog signal to the third memory circuit overlaps at least partially with a fourth period during which the fourth pixel outputs the analog signal to the fourth memory circuit; the control circuit controls the memory control circuit such that, during the single frame, the first memory circuit, the second memory circuit, the third memory circuit, and the fourth memory circuit sequentially output the analog signal to the analog-to-digital conversion circuit; and the first period does not overlap with the third period (the claim is related to a manner of operating the sensor, as Onuki teaches all of the structures, as already discussed prior, Onuki anticipates the claims as the manner of operating the device does not differentiate it over the prior art if all of the structure is discloses – See MPEP 2114).
With respect to claim 12 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 9, wherein: the first pixel and the second pixel each have a photoelectric conversion element (313) configured to generate charge in response to incident light and a transfer transistor (314) configured to transfer the charge (Fig. 2D); and the control circuit controls the pixel control circuit such that, during the single frame, a period in which the transfer transistor included in the first pixel is on during the first period overlaps at least partially with a period in which the transfer transistor included in the second pixel is on during the second period (the claim is related to a manner of operating the sensor, as Onuki teaches all of the structures, as already discussed prior, Onuki anticipates the claims as the manner of operating the device does not differentiate it over the prior art if all of the structure is discloses – See MPEP 2114).
With respect to claim 15 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the analog signal includes a reset-level signal and a photoelectric conversion signal, and a memory circuit included in the memory array has a first capacitive element configured to retain the reset-level signal and a second capacitive element configured to retain the photoelectric conversion signal (paragraph 95-96, 114 and 125-128; where the imager does CDS which requires an output reset and image signal to difference to remove noise).
With respect to claim 16 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein, in a plan view with respect to the first substrate, a bonding portion of the first substrate and the second substrate is disposed at a position overlapping at least partially with the pixel array (Fig. 7 and paragraph 263).
With respect to claim 17 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the first substrate has a first metal part and a first insulating film, and the second substrate has a second metal part and a second insulating film; and on a bonding surface between the first substrate and the second substrate, a bonding portion of the first metal part and the second metal part, and a bonding portion of the first insulating film and the second insulating film, are disposed (Fig. 7 and paragraph 245-260).
With respect to claim 18 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the second substrate has a plurality of the memory control circuits (Fig. 1B).
With respect to claim 19 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 1, wherein the first substrate or the third substrate has a plurality of the pixel control circuits (paragraph 71-74).
With respect to claim 20 Onuki discloses, in Fig. 1A-16C, Equipment (Fig. 12A-D and 13 and paragraph 334-342) comprising: the photoelectric conversion apparatus according to claim 1 (paragraph 334), the equipment further comprising at least one of: an optical device configured to direct light to the photoelectric conversion apparatus (Fig. 12A-D); a control device configured to control the photoelectric conversion apparatus (Fig. 12A-13); a processing device configured to process a signal output from the photoelectric conversion apparatus (paragraph 340-341); a display device configured to display information obtained by the photoelectric conversion apparatus (Fig. 12D); a storage device configured to store information obtained by the photoelectric conversion apparatus (Fig. 12B-C); or a mechanical device configured to operate based on information obtained by the photoelectric conversion apparatus (Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2020/0303444 A1 to Onuki et al.
With respect to claim 13 Onuki discloses, in Fig. 1A-16C, the photoelectric conversion apparatus according to claim 9 (see above), wherein: the pixels only have one photodiode per pixel readout circuit (See Fig. 2D) but Onuki states the pixels should not be limited to this arrangement (paragraph 132-133).
That is Onuki does not expressly disclose the first pixel and the second pixel each have a first photoelectric conversion element configured to generate a first charge in response to incident light, a first transfer transistor configured to transfer the first charge, a second photoelectric conversion element configured to generate a second charge in response to incident light, and a second transfer transistor configured to transfer the second charge; and the control circuit controls the pixel control circuit such that, during the single frame, a period in which the first transfer transistor and the second transfer transistor included in the first pixel are on during the first period overlaps at least partially with a period in which the first transfer transistor and the second transfer transistor included in the second pixel are on during the second period.
However, the structure of this claim can be satisfied if Onuki had a shared pixel readout for two or more photodiodes. These pixel types are well known and expected in the art to the point where they have their own classification symbol (H04N25/778). (note: the additional claim limitations are a manner of operating the device, see MPEP 2114)
Therefore, Official Notice (MPEP § 2144.03) is taken that both the concepts and advantages of providing multiple photodiodes for a single pixel that then share a source follower and have transfer transistors for each photodiode are well known and expected in the art. Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to have included such a pixel as it would merely be a simple substitution of one known element for another to obtain predictable results.
Claim 14 is rejected for similar reasons as claim 13 above with respect to wherein a pixel included in the pixel array has a plurality of photoelectric conversion elements configured to generate charge in response to incident light
Onuki does not express disclose the memory array retains the analog signal corresponding to a charge obtained by adding a plurality of charges respectively generated by the plurality of photoelectric conversion elements (i.e. binning pixels). However, binning pixels is a manner of operating a circuit as the claim does not further limit the structure in anyway the Examiner has no reason to believe the claimed structures are not provided for the binning functionality as you would merely need to read out both stored signals at the same time (i.e. See above discussion as related to MPEP 2114 about the manner of operating a device distinguishing over the art). However, should there be inherent required structures the examiner is overlooking Official Notice (MPEP § 2144.03) is taken that both the concepts and advantages of binning pixel signals in memory circuits of an imager are well known and expected in the art. Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to have included such a pixel as it would merely be a simple substitution of one known element for another to obtain predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication 2019/0297287 A1 to Oka et al which also discloses three stacked substrates where the top is a pixel array, middle is a memory and bottom has and ADC.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M PASIEWICZ whose telephone number is (571)272-5516. The examiner can normally be reached M-F 9 AM - 5:30 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, George Eng can be reached at (571)272-7495. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL M PASIEWICZ/Primary Examiner, Art Unit 2699
August 18, 2026
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