DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responding to the restriction election made on 06/05/2026. Claims 17-24 are withdrawn. Claims 1-16 and 25 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-14, 16 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. [US 11,037,630 B2] in view of Fai et al. [US 8,472,274 B2].
Claim 1 is rejected over Muchherla and Fai.
Muchherla teaches “A memory system, comprising: one or more memory devices comprising non-volatile memory cells; and” as “ For purposes of the present description example memory operation and management functions will be described in the context of NAND memory. Persons skilled in the art will recognize that other forms of non-volatile memory may have analogous memory operations or management functions.” [Col 6, lines 13-18]
“processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:” as “The memory array 600 can be accessed (e.g., by a control circuit, one or more processors, digital logic, etc.) using one or more drivers.” [Col 11, lines 15-20]
“receive a command to provide write temperature information associated with data written to the one or more memory devices;” as “At operation 805, a controller of a NAND device receives a command to write data to a NAND component in the NAND device. At operation 810, a temperature corresponding to the NAND component is obtained in response to receiving the command. In an example, obtaining the temperature includes obtaining the temperature from a thermometer in response to receiving the command.” [Col 13, lines 59-66]
Muchherla does not explicitly teach read, from the one or more memory devices based at least in part on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data; and
read, based at least in part on transmitting the write temperature to a host system, one or more subsets of the data.
However, Fai teaches “read, from the one or more memory devices based at least in part on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data; and” as “ a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells.” [Col 1, lines 48-55]
“read, based at least in part on transmitting the write temperature to a host system, one or more subsets of the data.” as “ a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells.” [Col 1, lines 48-55]
Muchherla and Fai are analogous arts because they teach data management in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Muchherla and Fai before him/her, to modify the teachings of Muchherla to include the teachings of Fai with the motivation of the temperature of NVM can be more accurately determined by using temperature sensors located in and around the NVM. [Fai, Col 2, lines 25-27]
Claim 2 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is further configured to cause the memory system to: receive a read command for one or more subsets of the data; and” as “ the data is read in response to receiving a read command at the controller 210. ” [Col 8, lines 53-54]
“transmit, based at least in part on receiving the read command, an indication that the one or more subsets of the data is unrecoverable at a current temperature of the memory system, wherein the command to provide write temperature information is received based at least in part on the indication.” as “the controller may even use the stored temperature to correct read voltages in order to avoid errors in the first place. In an example, because pages are generally the smallest addressable portion of a flash array, the controller may read each page upon startup, perform error correction to recover the temperature information, and cache the temperature of each block to either correct read voltages or provide the temperature to a host to then correct read voltages.” [Col 4, lines 48-56]
Claim 3 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is further configured to cause the memory system to: determine whether a current temperature of the memory system is within a threshold range of the write temperature, wherein the one or more subsets of the data is read based at least in part on determining that the current temperature of the memory system is within the threshold range of the write temperature.” as “ In Example 29, the subject matter of Example 28 includes, wherein the maintenance operation is a refresh of the NAND component, and wherein modifying the maintenance operation includes adjusting thresholds to perform the refresh based on the representation of the temperature.” [Col 19, lines 40-45]
Claim 4 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is further configured to cause the memory system to: receive, from the host system, an indication that the host system has adjusted a temperature setting associated with the memory system, wherein the current temperature is determined based at least in part on the indication.” as “ In an example, modifying the maintenance operation includes adjusting thresholds to perform the refresh based on the representation of the temperature.” [Col 8, line 65-Col 9, line 1]
Claim 5 is rejected over Muchherla and Fai.
Muchherla does not explicitly teach wherein the processing circuitry is further configured to cause the memory system to: receive, from the host system, an indication that the current temperature of the memory system is within the threshold range of the write temperature, wherein determining that the current temperature of the memory system is within the threshold range is based at least in part on the indication.
However, Fai teaches “wherein the processing circuitry is further configured to cause the memory system to: receive, from the host system, an indication that the current temperature of the memory system is within the threshold range of the write temperature, wherein determining that the current temperature of the memory system is within the threshold range is based at least in part on the indication.” as “ if the temperature of the NVM exceeds a threshold level above which MLC mode is less reliable, then the data can be written in SLC mode. In contrast, if the temperature of the NVM is below a threshold level at which MLC programming is sufficiently reliable, then the data can be written in MLC mode.” [Col 13, lines 40-46]
Claim 6 is rejected over Muchherla and Fai.
Muchherla does not explicitly teach wherein the processing circuitry is further configured to cause the memory system to: receive a read command for the one or more subsets of the data based at least in part on transmitting the write temperature, wherein the one or more subsets of the data is read based at least in part on the read command.
However, Fai teaches “wherein the processing circuitry is further configured to cause the memory system to: receive a read command for the one or more subsets of the data based at least in part on transmitting the write temperature, wherein the one or more subsets of the data is read based at least in part on the read command.” as “ a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells.” [Col 1, lines 48-55]
Claim 7 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is configured to cause the memory system to: determine a first logical address associated with a most-recently written subset of the data; and” as “ a page of data having a page size of 4 KB may include 4 KB of user data (e.g., 8 sectors assuming a sector size of 512 B) as well as a number of bytes (e.g., 32 B, 54 B, 524 B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detecting or correcting code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.” [Col 7, lines 32-38]
Muchherla does not explicitly teach transmit an indication of the first logical address associated with the most- recently written subset of the data, wherein the read command is received based at least in part on transmitting the indication.
However, Fai teaches “transmit an indication of the first logical address associated with the most- recently written subset of the data, wherein the read command is received based at least in part on transmitting the indication.” as “ As described above with regard to FIG. 1, stored temperature information can be metadata that describes the temperature of one or more portions of NVM (e.g., die, block, page, memory cells) at or around the time data was most recently written to the portions of the NVM.” [Col 11, lines 40-45]
Claim 9 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the write temperature is associated with a first logical address and the command is associated with a second logical address, and wherein the processing circuitry is further configured to cause the memory system to:” as “ a page of data having a page size of 4 KB may include 4 KB of user data (e.g., 8 sectors assuming a sector size of 512 B) as well as a number of bytes (e.g., 32 B, 54 B, 524 B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detecting or correcting code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.” [Col 7, lines 32-38]
Muchherla does not explicitly teach read the write temperature from memory cells associated with the first logical address based at least in part on the first logical address satisfying a substitution condition for returning the write temperature to the host system in place of a second write temperature associated with the second logical address.
However, Fai teaches “read the write temperature from memory cells associated with the first logical address based at least in part on the first logical address satisfying a substitution condition for returning the write temperature to the host system in place of a second write temperature associated with the second logical address.” as “ a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells.” [Col 1, lines 48-55]
Claim 10 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is further configured to cause the memory system to: determine whether the second write temperature is unrecoverable, wherein the write temperature is read based at least in part on determining that the second write temperature is unrecoverable.” as “ the controller may even use the stored temperature to correct read voltages in order to avoid errors in the first place. In an example, because pages are generally the smallest addressable portion of a flash array, the controller may read each page upon startup, perform error correction to recover the temperature information, and cache the temperature of each block to either correct read voltages or provide the temperature to a host to then correct read voltages.” [Col 4, lines 48-56]
Claim 11 is rejected over Muchherla and Fai.
Muchherla does not explicitly teach wherein the processing circuitry is configured to cause the memory system to: determine that the first logical address satisfies the substitution condition based at least in part on the first logical address being within a threshold range, index-wise, of the second logical address.
However, Fai teaches “wherein the processing circuitry is configured to cause the memory system to: determine that the first logical address satisfies the substitution condition based at least in part on the first logical address being within a threshold range, index-wise, of the second logical address.” as “ the host controller 102 can provide a request for a media file (e.g., audio file) to the NVM package 104. Such a request provided by the host controller 102 can include one or more logical addresses corresponding to the media file.” [Col 4, lines 12-16]
Claim 12 is rejected over Muchherla and Fai.
Muchherla does not explicitly teach wherein the processing circuitry is configured to cause the memory system to: determine that the first logical address satisfies the substitution condition based at least in part on a performance level assigned to a first physical address associated with the first logical address.
However, Fai teaches “wherein the processing circuitry is configured to cause the memory system to: determine that the first logical address satisfies the substitution condition based at least in part on a performance level assigned to a first physical address associated with the first logical address.” as “in response to receiving a request specifying a logical address of a media file to be retrieved, the memory controller 114 can identify one or more corresponding physical addresses (e.g., information identifying die, block, and/or page), retrieve the requested data using the identified physical addresses,” [Col 4, line 63- col 5, line 1]
Claim 13 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the processing circuitry is configured to cause the memory system to: determine that the first logical address satisfies the substitution condition based at least in part on a physical location of memory cells associated with the first logical address.” as “ The controller 210 is arranged to read the data from the NAND component and is also arranged to read the representation of the temperature when the data is read. In an example, reading the data is in response to a power-on condition of the managed memory device 205.” [Col 8, lines 41-45]
Claim 14 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the command indicates a first logical address, and wherein the processing circuitry is further configured to cause the memory system to: determine a table of the one or more memory devices that stores write temperatures representative of average write temperatures for different subsets of the data;” as “ FIGS. 4A-4B illustrate storage configurations for NAND temperature data. FIG. 4A illustrates an organization where a dedicated portion of the page is set-aside for controller metadata. Thus, the page is divided in the user data portion 405 and the auxiliary bytes portion 410.” [Col 9, lines 34-38]
“and read the write temperature from the table based at least in part on the write temperature being associated with a range of logical addresses that includes the first logical address.” as “ In contrast, FIG. 4B illustrates an alternative organization in which the auxiliary bytes are interspersed throughout the use data segments, resulting in a heterogenous portion 415. However, the “INFO” auxiliary bytes 420 are still located on the page and can store the temperature data of the page when it was last written.” [Col 9, lines 40-45]
Claim 16 is rejected over Muchherla and Fai.
Muchherla teaches “wherein the command is associated with a first logical address, and wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on the first logical address, a table in the one or more memory devices that stores the write temperature associated with the first logical address, wherein the write temperature is read from the table.” as “ An SSD can include a number of memory devices, including a number of dies or logical units (e.g., logical unit numbers or LUNs), and can include one or more processors or other controllers performing logic functions required to operate the memory devices or interface with external systems. ” [Col 2, line 66-Col 3, line 4]
Claim 25 is rejected over Muchherla and Fai under the same rationale of rejection of claim 1.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. [US 11,037,630 B2] in view of Fai et al. [US 8,472,274 B2] and in further view of Zhou et al. [US 11,768,615 B1].
Claim 15 is rejected over Muchherla, Fai and Zhou.
The combination of Muchherla and Fai does not explicitly teach wherein the processing circuitry is further configured to cause the memory system to: write the subset of the data to the one or more memory devices, wherein the command to provide the write temperature information is received after writing the subset of the data;
determine an average write temperature for the subset of the data based at least in part on writing the subset of the data and based at least in part on a size of the subset of the data satisfying a threshold; and
write the write temperature to the table of the one or more memory devices, wherein the write temperature comprises the average write temperature.
However, Zhou teaches “wherein the processing circuitry is further configured to cause the memory system to: write the subset of the data to the one or more memory devices, wherein the command to provide the write temperature information is received after writing the subset of the data;” as “ different memory management operations can be performed on different groups of memory cells within each memory component 112A to 112N based on deviations between the write temperatures and the corresponding temperature thresholds associated with the respective memory component 112A to 112N.” [Col 8, lines 12-18]
“determine an average write temperature for the subset of the data based at least in part on writing the subset of the data and based at least in part on a size of the subset of the data satisfying a threshold; and” as “The write temperature module 230 can compute an average or mean or some other statistical representation of the plurality of write temperatures. The media operations manager 200 determine that the average or mean or some other statistical representation of the plurality of write temperatures associated with the first group of memory components 112A to 112N falls within a range of the temperature values associated with the temperature threshold stored in the configuration data 220. ” [Col 12, lines 40-56]
“write the write temperature to the table of the one or more memory devices, wherein the write temperature comprises the average write temperature.” as “a memory or register can be associated with all of the memory components 112A to 112N that can store a table that maps different groups, bins or sets of the memory components 112A to 112N to respective temperature thresholds.” [Col 6, lines 39-44]
Muchherla, Fai and Zhou are analogous arts because they teach data management in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Muchherla, Fai and Zhou before him/her, to modify the teachings of combination of Muchherla and Fai to include the teachings of Zhou with the motivation of the controller to dynamically select and tailor different media management operations to the temperature threshold of the corresponding group of memory components, which improves the overall efficiency of operating the memory sub-system. [Zhou, Col 2, lines 8-13]
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including Muchherla et al. (US 11,037,630 B2) and Fai et al. (US 8,472,274 B2), fails to teach or suggest wherein the data comprises black box data received from one or more vehicle sensors and wherein the read command is part of a forensic data recovery procedure to recover the black box data.
Muchherla is directed to storage management and data recovery operations within a memory system, but does not disclose recovering event recorder or black box data originating from vehicle sensors, nor does Muchherla disclose issuing read commands as part of a forensic investigation or post-event forensic recovery procedure. Fai discloses vehicle event data recording and storage of vehicle operational information; however, Fai does not teach a memory-system read command that is specifically performed as part of a forensic data recovery procedure for recovering black box data from memory. The cited references, either alone or in combination, merely disclose storage and retrieval of data and/or vehicle event recording, but do not disclose or suggest the claimed integration of a forensic recovery operation in which read commands are executed to recover black box data obtained from vehicle sensors for forensic analysis.
Accordingly, the claimed subject matter is considered allowable because the prior art of record does not teach or render obvious the use of a read command as part of a forensic data recovery procedure to recover vehicle-sensor-derived black box data.
Conclusion
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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