DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 4, 5, 9, 12, 13, 15 and 16 of U.S. Patent 12,282,675 contains every element of claims 2, 3, 6, 7 and 9-20 of the instant application and as such anticipates claims 2, 3, 6 and 9-20 of the instant application.
Claims 2 and 19 of the instant application are anticipated by claims 1 and 13, claims 3, 6, 9, 10 and 20 of the instant application are anticipated by claim 16, claims 7 and 17 of the instant application are anticipated by claim 12, claim 11 of the instant application is anticipated by claim 13, claims 12, 14 and 15 of the instant application are anticipated by claim 1, claim 13 of the instant application is anticipated by claims 15 and 16, claim 16 of the instant application is anticipated by claim 9, claim 18 of the instant application is anticipated by claims 4 and 5.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-7 and 9-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raj et al. (US 2018/0089099).
Consider claim 2, Raj et al. discloses a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: store, at a set of memory cells having one or more physical addresses, data associated with one or more first addresses within an address space; receive, after storing the data at the set of memory cells, a copy command for the data; associate, in response to the copy command, the data with one or more second addresses within the address space; and update one or more mapping tables within the memory system to associate the one or more second addresses with the one or more physical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the use of copy commands that move data at one address to another address. Logical addressing is used and mapping tables are updated.).
Consider claim 3, Raj et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: associate the one or more physical addresses with both the one or more second addresses and the one or more first addresses after the data is associated with the one or more physical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses Logical addressing is used and mapping tables are updated. A chain of descriptors and thus copy operations can be performed which includes associations with a plurality of addresses.).
Consider claim 4, Raj et al. discloses the memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: write one or more flags to the one or more mapping tables to indicate that the one or more physical addresses are associated with both the one or more second addresses and the one or more first addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses that the mapping tables include indications of associations between addresses.).
Consider claim 5, Raj et al. discloses the memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: store, in an array of metadata, one or more flags that indicate that the one or more physical addresses are associated with both the one or more second addresses and the one or more first addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses that the mapping tables include indications associations between addresses.).
Consider claim 6, Raj et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: associate, using a second mapping table within the memory system, the one or more first addresses with the one or more second addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses that the mapping tables include indications associations between addresses.).
Consider claim 7, Raj et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive an access command associated with a portion of the data stored at the set of memory cells; and read a portion of the one or more mapping tables in response to receiving the access command, wherein the portion of the one or more mapping tables comprises one or more flags (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses copy commands being performed using mapping tables. The mapping tables include indications associations between addresses. One or more flags are considered to be whatever indicates the association between the addresses in the table.).
Consider claim 9, Raj et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: continue to store the data at the set of memory cells having the one or more physical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses storing data at physical addresses locations.).
Consider claim 10, Raj et al. discloses the memory system of claim 2, wherein the one or more first addresses comprise one or more first logical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses Logical addressing).
Consider claim 11, Raj et al. discloses the memory system of claim 2, wherein the one or more second addresses comprise one or more second logical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses Logical addressing).
Consider claim 12, Raj et al. discloses a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: store, within the one or more memory devices, data associated with one or more first addresses within an address space; receive a copy command comprising a numeric value that is representative of a length of a list of copy parameters associated with the copy command; receive, after receiving the copy command, the list of copy parameters, wherein the list of copy parameters has the length represented by the numeric value included in the copy command; and associate data with one or more second addresses within the address space based at least in part on receiving the copy command (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the use of copy commands that move data at one address to another address. Logical addressing is used and mapping tables are updated. The copy command includes opcode, source address, transfer length and destination address or a change of multiple descriptors having this information for a chain of copies.).
Consider claim 13, Raj et al. discloses the memory system of claim 12, wherein the processing circuitry is further configured to cause the memory system to: store, prior to receiving the copy command, the data at a set of memory cells; and continue to store, after associating the data with the one or more second addresses within the address space, the data at the set of memory cells (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the use of copy commands that move data at one address to another address. Logical addressing is used and mapping tables are updated.).
Consider claim 14, Raj et al. discloses the memory system of claim 13, wherein the list of copy parameters comprises the one or more first addresses and the one or more second addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the copy command includes opcode, source address, transfer length and destination address or a change of multiple descriptors having this information for a chain of copies.).
Consider claim 15, Raj et al. discloses the memory system of claim 12, wherein the length of the list of copy parameters is equal to a quantity of bytes represented by the numeric value included in the copy command (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the copy command includes opcode, source address, transfer length and destination address or a change of multiple descriptors having this information for a chain of copies.).
Consider claim 16, Raj et al. discloses the memory system of claim 12, wherein, to associate the data with the one or more second addresses, the processing circuitry is configured to cause the memory system to: associate the data with a set of sequential addresses that begins with a start address within the one or more second addresses, the start address being indicated by the list of copy parameters (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the copy command can include a chain of descriptors that a sequentially processed.).
Consider claim 17, Raj et al. discloses the memory system of claim 12, wherein the processing circuitry is further configured to cause the memory system to: read, in response to the copy command, the data from a first set of memory cells associated with the one or more first addresses; and write, in response to the copy command, a copy of the data to a second set of memory cells associated with the one or more second addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the use of copy commands that move data at one address to another address.).
Consider claim 18, Raj et al. discloses the memory system of claim 12, wherein the list of copy parameters comprises an indication of a quantity of information allocated to one or more block indicators each for a respective block of data, an indication of a quantity of information included in the list of copy parameters, an indication of a start address within the one or more second addresses, or any combination thereof (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the copy command includes opcode, source address, transfer length and destination address or a change of multiple descriptors having this information for a chain of copies.).
Consider claim 19, Raj et al. discloses a non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: store, at a set of memory cells having one or more physical addresses, data associated with one or more first addresses within an address space; receive, after storing the data at the set of memory cells, a copy command for the data; associate, in response to the copy command, the data with one or more second addresses within the address space; and update one or more mapping tables within a memory system to associate the one or more second addresses with the one or more physical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses the use of copy commands that move data at one address to another address. Logical addressing is used and mapping tables are updated.).
Consider claim 20, Raj et al. discloses the non-transitory computer-readable medium of claim 19 wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: associate the one or more physical addresses with both the one or more second addresses and the one or more first addresses after the data is associated with the one or more physical addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses Logical addressing is used and mapping tables are updated. A chain of descriptors and thus copy operations can be performed which includes associations with a plurality of addresses.).
Consider claim 21, Raj et al. discloses the non-transitory computer-readable medium of claim 19 wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: write one or more flags to the one or more mapping tables to indicate that the one or more physical addresses are associated with both the one or more second addresses and the one or more first addresses (Fig. 3, [0027]-[0028], [0052]-[0053], [0058]-[0063] and [0077]-[0078], Raj et al. discloses that the mapping tables include indications of associations between addresses.).
Allowable Subject Matter
Claims 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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