DETAILED ACTION
This office action is in response to the application filed on 04/08/2025. Claims 1-11 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 04/08/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/08/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9-10 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Murakami (US Patent or PG Pub. No. 20230087732, hereinafter ‘732).
Claim 1, ‘732 teaches a semiconductor device (e.g., see Fig. 3-11) comprising: a switch circuit (e.g., the circuits comprising Q4, 300) having at least one switch (e.g., Q4) configured as a MOSFET connected between two terminals of a specific element 1 (e.g. Q2, see Fig. 7, 9-11); and a leakage cancellation circuit (e.g., 220, see Fig. 4, 6-11) having at least one MOS transistor configured as a MOSFET, connected to the switch circuit at a specific node (e.g., N3/N4 or the reference ground), and configured to inject or extract a leakage current with respect to the specific node (e.g., 220, see Abstract, Fig. 4, 6-11).
Claim 2, ‘732 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the MOS transistor is configured as a MOSFET of a same polarity as the switch (e.g., see Fig. 7-11).
Claim 3, ‘732 teaches the limitations of claim 2 as discussed above. It further teaches that wherein in the switch circuit, a plurality of the switches (e.g., Q3, Q4) are connected in series, in the leakage cancellation circuit, a plurality of the MOS transistors are connected in series (e.g., see Fig. 4), and each of the plurality of the MOS transistors has a same configuration as each of the plurality of the switches (e.g., see Fig. 4, 7-11).
Claim 9, ‘732 teaches the limitations of claim 1 as discussed above. It further teaches that wherein in the leakage cancellation circuit, a plurality of the MOS transistors are connected in series (e.g., see Fig. 5), and the leakage cancellation circuit further comprises a transistor that is connected to the MOS transistor on a lowest potential side among the plurality of the MOS transistors and has a gate and a source short-circuited (e.g., the Leakage Circuit B and C, see Fig. 4B).
Claim 10, ‘732 teaches the limitations of claim 1 as discussed above. It further teaches that wherein in the leakage cancellation circuit, a plurality of the MOS transistors are connected in series, and a gate and a source of the MOS transistor on a lowest potential side among the plurality of the MOS transistors are short-circuited (e.g., the Leakage Circuit B and C, see Fig. 4B).
Allowable Subject Matter
Claims 4-8, 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 4, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “wherein respective gates of the plurality of the MOS transistors are connected to respective gates of the plurality of the switches”.
For claim 5, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “respective back gates of the plurality of the MOS transistors are connected to the specific node, and a source of the MOS transistor on a lowest potential side among the plurality of the MOS transistors is directly or indirectly connected to the specific node”.
For claim 6, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “respective back gates of the plurality of the MOS transistors are connected to an application terminal of a ground potential , and a source of the MOS transistor on a lowest potential side among the plurality of the MOS transistors are directly or indirectly connected to the specific node”.
For claim 7, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “respective back gates of the plurality of the MOS transistors are connected to an application terminal of a ground potential, a source of the MOS transistor on a lowest potential side among the plurality of the MOS transistors is directly or indirectly connected to the application terminal of the ground potential, the leakage cancellation circuit further comprises a first current mirror, and the first current mirror comprises: a first PMOS transistor having a drain connected to a drain of the MOS transistor on a highest potential side among the plurality of the MOS transistors; and a second PMOS transistor having a drain connected to the specific node”.
For claim 8, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “respective back gates of the plurality of the MOS transistors are connected to an application terminal of a specific voltage, a source of the MOS transistor on a highest potential side among the plurality of the MOS transistors is connected to the application terminal of the specific voltage, the leakage cancellation circuit further comprises a second current mirror, and the second current mirror comprises: a first NMOS transistor having a drain connected to a drain of the MOS transistor on a lowest potential side among the plurality of the MOS transistors; and a second NMOS transistor having a drain connected to the specific node”.
For claim 11, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a constant voltage generation circuit comprising: a first transistor stage configured by a plurality of first transistor parts as depletion-type N-channel MOSFETs connected in series; a second transistor stage 2 connected to the first transistor stage at the specific node, and configured by a plurality of second transistor parts as enhancement-type N-channel MOSFETs connected in series”, and “
the plurality of the switches are respectively connected between two terminals of each of the plurality of first transistor parts serving as the specific elements, or between two terminals of each of the plurality of second transistor parts serving as the specific elements”.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication US 20230037837 A1 discloses a voltage regulator with Leakage Compensation Circuit.
US Patent Application Publication US 20090140776 A1 discloses a Voltage-current Converter with Leakage current cancel Circuit.
US Patent Application Publication US 20020175733 A1 discloses a leak Current Cancel Circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUE ZHANG/
Primary Examiner, Art Unit 2838
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication US 2024/0106325 A1 discloses a SMPS chip and system for a solar photovoltaic panel for maximum power output.
Chinese Patent CN 109787270 B discloses a power optimization scheme for a voltage converter in a photovoltaic module converter.
Chinese Patent Application Publication CN 111092484 A discloses a DC/DC converter controller for maximum output power control of a solar cell.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2013/0002186, US 9,461,556, US 8,212,506, and US 6,341,078 all fail to teach or disclose the limitations indicated above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUE ZHANG/
Primary Examiner, Art Unit 2838
Prosecution Insights