DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/08/2025, 02/20/2026 and 07/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0003 “cannot appropriately drives” should be “cannot appropriately drive”.
Paragraph 0025 “using pn junction” should be “using a pn junction”.
Paragraph 0029 “semiconductor element 31A to 31C” should be “semiconductor elements 31A to 31C”.
Paragraph 0031 “using pn junction” should be “using a pn junction”.
Paragraph 0033 “holding structure 26A to 26C” should be “holding structures 26A to 26C”.
Appropriate correction is required.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2022/0416664 A1) in view of Park (US 2017/0163199 A1) and in further view of Imanishi (US 2019/0379298 A1).
Regarding claim 1, Wu teaches a power semiconductor drive device (Figure 4A), comprising: a controller receiving a command signal from an outer part and outputting a plurality of parallel signals (Figure 4B Component 422; Paragraph 0093 “This startup state of operation of the controller 422 may be initiated and controlled by a command signal generated within the power converter 400 or by externally supplied commands”); a plurality of drive circuits (Figure 4A Components 402) driving a plurality of power semiconductor elements each having reference potential different from each other (Figure 4A Components M1-M8), respectively; a plurality of level shift circuits connected between the controller and the plurality of drive circuits (Figure 4A Components 404) and level-shifting the plurality of parallel signals in accordance with the reference potential of the plurality of power semiconductor elements, respectively (Paragraphs 0052-0054; Figure 4A Components 404 level shift the received respective parallel signal and the level shifter is connected with the reference potential of the respective power semiconductor element).
Wu does not teach a conversion circuit converting a serial signal from an outer part into a plurality of parallel signals; and a voltage holding structure electrically separating each of the plurality of drive circuits.
Park teaches a circuit (Figure 2), comprising: a conversion circuit converting a serial signal from an outer part into a plurality of parallel signals (Figure 2 Component 111 receives Component SPI from Component 105 and converts the serial PWM signal into a plurality of parallel signals that supplied to the driver, Component 112; Paragraph 0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu to incorporate the serial-to-parallel interface as taught by Park. The advantage of this modification is that there would be a reduction of external wiring and pin count while also simplifying the synchronization and coordinated control of Wu’s multiple power switch channels.
Imanishi teaches a circuit (Figure 8), comprising: a plurality of drive circuits (Figure 8 Components 340a and 340b) driving a plurality of semiconductor elements (Figure 8 Components 310a and 310b); each power semiconductor elements having a reference potential different from each other (Paragraph 0078-0080); level shift circuit connected between the controller and the driver circuit (Figure 8 Component 330); and a voltage holding structure electrically separating each of the plurality of drive circuits (Figure 2-3 and Paragraphs 0032-0040 disclose low voltage region AR1 and high voltage region AR2 are separated by holding portion 250 on substrate 200; Figures 4-6 and Paragraphs 0045-0064 disclose drive circuit 110 is in low voltage region AR1 and drive circuit 120 is in high voltage region AR2; Magnetic coupling element 140 transmits the control signal between separated regions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu to incorporate the breakdown voltage holding isolation structure taught by Imanishi. The advantage is that the respective drive circuit are isolated from the different reference potentials thus improving high voltage withstand capability and reducing signal transfer loss and noise.
Regarding claim 2, Wu, Park and Imanishi teach all the limitations of claim 1. Wu does not teach wherein the conversion circuit, the plurality of drive circuits, the plurality of level shift circuits, and the voltage holding structure are provided on one semiconductor substrate.
Imanishi teaches a circuit (Figure 8), comprising: a plurality of drive circuits (Figure 8 Components 340a and 340b) driving a plurality of semiconductor elements (Figure 8 Components 310a and 310b); each power semiconductor elements having a reference potential different from each other (Paragraph 0078-0080); level shift circuit connected between the controller and the driver circuit (Figure 8 Component 330); and a voltage holding structure electrically separating each of the plurality of drive circuits (Figure 2-3 and Paragraphs 0032-0040 disclose low voltage region AR1 and high voltage region AR2 are separated by holding portion 250 on substrate 200; Figures 4-6 and Paragraphs 0045-0064 disclose drive circuit 110 is in low voltage region AR1 and drive circuit 120 is in high voltage region AR2; Magnetic coupling element 140 transmits the control signal between separated regions), wherein the conversion circuit, the plurality of drive circuits, the plurality of level shift circuits, and the voltage holding structure are provided on one semiconductor substrate (Figure 3 all components are provided on one substrate, Component 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu to incorporate the breakdown voltage holding isolation structure taught by Imanishi. The advantage is that the respective drive circuit are isolated from the different reference potentials thus improving high voltage withstand capability and reducing signal transfer loss and noise.
Regarding claim 4, Wu, Park and Imanishi teach all the limitations of claim 1. Wu does not teach wherein the voltage holding structure includes a structure using dielectric isolation.
Imanishi teaches a circuit (Figure 8), comprising: a plurality of drive circuits (Figure 8 Components 340a and 340b) driving a plurality of semiconductor elements (Figure 8 Components 310a and 310b); each power semiconductor elements having a reference potential different from each other (Paragraph 0078-0080); level shift circuit connected between the controller and the driver circuit (Figure 8 Component 330); and a voltage holding structure electrically separating each of the plurality of drive circuits (Figure 2-3 and Paragraphs 0032-0040 disclose low voltage region AR1 and high voltage region AR2 are separated by holding portion 250 on substrate 200; Figures 4-6 and Paragraphs 0045-0064 disclose drive circuit 110 is in low voltage region AR1 and drive circuit 120 is in high voltage region AR2; Magnetic coupling element 140 transmits the control signal between separated regions), wherein the voltage holding structure includes a structure using dielectric isolation (Paragraph 0063).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu to incorporate the breakdown voltage holding isolation structure taught by Imanishi. The advantage is that the respective drive circuit are isolated from the different reference potentials thus improving high voltage withstand capability and reducing signal transfer loss and noise.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2022/0416664 A1) in view of Park (US 2017/0163199 A1) and in further view of Imanishi (US 2019/0379298 A1) and in further view of Honda (US 9431479 B2).
Regarding claim 3, Wu, Park and Imanishi teach all the limitations of claim 1. Wu does not teach wherein the voltage holding structure includes a high-voltage RESURF structure using pn junction.
Honda teaches a high-breakdown voltage semiconductor device containing a RESURF layer (Figure 1; Col. 4 Line 52 – Col. 5 Line 4 discloses an n-type semiconductor substrate 7 and p-type RESURF layer, Component 9, formed in the substrate and surrounding electrode layer wherein the interface between p-type RESURF layer 9 and n-type substrate 7 form a PN junction; Col. 14 Lines 49-59 state that the RESURF structure is applicable to high-breakdown voltage devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wu to incorporate the high-voltage RESURF structure taught by Honda. The advantage of this modification is that it would improve the breakdown-voltage capability between differently referenced drive circuit regions.
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the conversion circuit is provided to a first semiconductor chip, the plurality of drive circuits and the voltage holding structure are provided to a second semiconductor chip insulated from the first semiconductor chip, and each of the plurality of level shift circuits includes a coupled circuit transmitting a signal from the first semiconductor chip to the second semiconductor chip while keeping insulation between the first semiconductor chip and the second semiconductor chip.
Claims 6-8 depend upon claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kondou (US 2014/0306674 A1) teaches a charge and discharge signal circuit that includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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