DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 04/09/25 has been considered by the examiner.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
4. The disclosure is objected to because of the following informalities: on lines 2-3 of paragraph [0001], the phrase "content of the application is" should be changed to
--contents of this application are--. On lines 3-4 of paragraph [0005], "embodiment that is" should be changed to --embodiments that are--. On line 3 of paragraph [0023], the word --is-- should be inserted at the end of the line after "but", and note that the same insertion is also needed on line 11 of this paragraph, again after the word "but". On line 25 of paragraph [0023], the word "this" should be changed to --these--. On line 29 of paragraph [0036], the first occurrence of the word "the" should be changed to --this--. On line 12 of paragraph [0038], the first occurrence of the word "the" should again be changed to --this--, and note that the same should also be made on line 16 of paragraph [0039], again before the word "embodiment". On line 16 of paragraph [0041], the second occurrence of the word "the" should again be changed to --this--, and note that the same change should also be made on line 19 of paragraph [0043]. On line 3 of paragraph [0045], the word "at" should be changed to --for--.
Appropriate correction is required.
Drawings
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the next-stage circuit comprising a conductor, a resistor, a transistor, and/or a switch element, as recited in claim 8, must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(b)
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
On the second line of claim 15, "the first transistor" lacks basis, the reason being that neither claim 1 nor claim 7 recites any first transistor (note that "a first transistor" is introduced in claim 2, but claim 15 does not go back to claim 2, either directly or indirectly).
On the third line of claim 15, "the first end of the storage capacitor" lacks antecedent basis, the reason being that neither claim 1 nor claim 7 recites any first end of any storage capacitor (note that "a storage capacitor" having a first end is introduced in claim 4, but claim 15 does not go back to claim 4, either directly or indirectly).
Claims 16-20 are rejected as being indefinite in view of their dependencies, directly or indirectly, on indefinite claim 15.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goyal et al, U.S. Patent Application Publication No. 2009/0243693.
As to claim 1, Goyal et al discloses, in figure 3,
an electronic circuit, comprising:
an output circuit (the output circuit in figure 3 of Goyal et al which includes pull-up transistor 322) comprising at least one first output transistor (transistor 322), the at least one first output transistor comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal); and
a first switch transistor (transistor 321) comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal), wherein the at least one first output transistor and the first switch transistors are complementary transistors (note that transistor 322 is a PMOS transistor and transistor 321 is an NMOS transistor);
wherein the first end (drain or source terminal) of the first switch transistor is coupled to the control end (gate terminal) of the at least one first output transistor; and
wherein during a specific duration, the first switch transistor is turned off, and the control end (gate terminal) of the at least one first output transistor is in a floating state (note that when transistor 321 is turned off, the gate voltage of transistors 322 and 323 will be floating as indicated in paragraph [0025] of Goyal et al and therefore transistors 322, 323 and 326 will all be off, and if the input data at terminal 315 is high logic level, transistor 327 will also be off, thereby placing output transistor 322 in a floating state).
As to claims 2 and 3, the claimed first transistor can be read on transistor 323.
As to claim 7, the claimed another first output transistor can be read on transistor 325.
As to claim 8, the claimed next-stage circuit can be read on the combination of transistors 324 and 325.
As to claim 9, note that when transistor 321 is turned off, a voltage at the gate terminal of transistor 322 appears to change with a voltage at the first end thereof, note that it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971)).
8. Claims 1-3, 7-9, 15 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nair, U.S. Patent No. 6,690,222.
As to claim 1, Nair discloses, in figure 2,
an electronic circuit, comprising:
an output circuit (the output circuit in figure 2 of Nair which includes transistors 5 and 6) comprising at least one first output transistor (transistor 5 or transistor 6), the at least one first output transistor comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal); and
a first switch transistor (transistor 2) comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal), wherein the at least one first output transistor and the first switch transistors are complementary transistors (note that outputs transistors 5 and 6 are PMOS transistors, whereas transistor 2 is an NMOS transistor);
wherein the first end (drain or source terminal) of the first switch transistor is coupled to the control end (gate terminal) of the at least one first output transistor; and
wherein during a specific duration, the first switch transistor is turned off, and the control end of the at least one first output transistor is in a floating state (note that when transistor 2 is turned off, the gate voltage of transistors 5 and 6 will be floating as indicated at column 5, lines 15-20, and therefore transistors 5 through 8 will all be off, and if the input data at terminal 1 is high logic level, transistor 4 will also be off, thereby placing output transistors 5 and 6 in a floating state).
As to claims 2 and 3, the claimed first transistor can be read on either transistor 7 or transistor 8.
As to claim 7, the claimed another first output transistor can be read on transistor 11.
As to claim 8, the claimed next-stage circuit can be read on the combination of transistors 11 and 12.
As to claim 9, note that when transistor 2 is turned off, a voltage at the gate terminal of transistors 5 and 6 appears to change with a voltage at the first end of these two transistors, as noted above it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971)).
As to claim 15, the claimed storage capacitor can be read on capacitor 15 shown in figure 2 of Nair.
As to claim 16, note that transistors 5 and 6 of Nair are PMOS transistors and transistor 2 is an NMOS transistor.
9. Claims 1-3 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dobberpuhl, U.S. Patent No. 5,160,855.
As to claim 1, Dobberpuhl discloses, in figure 3,
an electronic circuit, comprising:
an output circuit (the output circuit in figure 3 of Dobberpuhl which includes pull-up transistor Q5) comprising at least one first output transistor (transistor Q5), the at least one first output transistor comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal); and
a first switch transistor (transistor Q6, see figure 6) comprising a control end (gate terminal), a first end (drain or source terminal), and a second end (source or drain terminal), wherein the at least one first output transistor and the first switch transistors are complementary transistors (note that transistor Q5 is a PMOS transistor and transistor Q6 is an NMOS transistor);
wherein the first end (drain or source terminal) of the first switch transistor is coupled to the control end (gate terminal) of the at least one first output transistor; and
wherein during a specific duration, the first switch transistor is turned off, and the control end of the at least one first output transistor is in a floating state (note that when transistor Q6 is turned off, the gate voltage of transistor Q5 will be floating and therefore transistor Q5 will be in a floating state).
As to claims 2 and 3, the claimed first transistor can be read on the NMOS transistor shown in figure 3 of Dobberpuhl which receives supply voltage Vdd at its gate terminal.
As to claim 7, the claimed another first output transistor can be read on transistor Q8 shown in figure 6 of Dobberpuhl.
As to claim 8, the claimed next-stage circuit can be read on the circuit labeled VFW CIRCUITRY or, alternatively, the NMOS transistor shown in figure 3 of Dobberpuhl which receives supply voltage Vn at its gate terminal.
As to claim 9, note that when transistor Q6 is turned off, a voltage at the gate terminal of transistor Q5 appears to change with a voltage at the first end thereof, as noted above it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971)).
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over either Goyal et al or Dobberpuhl, supra.
As to claim 15, although neither Goyal et al nor Nair discloses a storage capacitor wherein the gate terminal of the first transistor in each of these references is coupled to a first end of the storage capacitor, such would have been obvious to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention to include a storage capacitor having its top plate coupled directly to the gate terminal of a field effect transistor in an integrated circuit and its bottom plate coupled directly to the ground, for the well-known purpose of filtering any potential noise spikes that may occur at the gate terminal of the transistor, of which fact official notice is taken by the examiner.
As to claim 16, note that the first transistor and the first output transistor in both Goyal et al and Dobberpuhl are complementary transistors, as noted above.
Allowable Subject Matter
11. Claims 4-6 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record discloses or suggests the electronic circuit of claim 1 with the further limitations of a data switch and a storage capacitor wherein a first end of the data switch receives a data voltage and a second end of the data switch is coupled to a first end of the storage capacitor and a control end of the first transistor, as recited in claims 4 and 10. Claims 5 and 6 are allowable in view of their dependencies, directly or indirectly, on allowable claim 4. Claims 11-14 are allowable in view of their dependencies, directly or indirectly, on allowable claim 10. Claim 17 is allowable in view of the limitations in this claim of a first inverter having an input coupled to the first end of the storage capacitor and an output coupled to the second end of the first switch transistor. Claims 18-20 are allowable in view of their dependencies, directly or indirectly, on allowable claim 17.
Prior Art Not Relied Upon
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Each of figure 2 of Cullen et al (USP 4,956,691) and figure 1 of Monk et al (USP 5,729,157) is also seen to anticipate at least independent claim 1, i.e., in figure 2 of Cullen et al the claimed first output transistor can be read on transistor 38 and the claimed first switch transistor can be read on transistor 22 (note that node 50 will be floating when transistor 22 is turned off, as indicated in column 4, lines 5-12, of Cullen et al), and in figure 1 of Monk et al the claimed first output transistor can be read on transistor 2 and the claimed first switching transistor can be read on transistor 8 (note that the gate voltage of transistor 2 will be floating when transistor 8 is turned off, as indicated at column 2, lines 55-57, of Monk et al).
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 June 26, 2026
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