DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 4-6, 8, 12-13, 15-17, 19-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more. The claims recite mathematical concepts and mental processes. This judicial exception is not integrated into a practical application because the claims generally link abstract ideas to a generic computer. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they include mere instructions to perform mathematical concepts and mental processes on a generic computer without creating a significant improvement or change to the computer.
Regarding Claim 1,
Step 2A Prong 1: Identification of Abstract Ideas
wherein the memory controller includes: at least one safety mechanism configured to determine at least one memory device fault condition that has a potential to adversely affect performance of at least one of the one or more memory device functions, (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and at least one safety mechanism monitor configured to determine at least one safety mechanism fault condition that has a potential to adversely affect an ability of the at least one safety mechanism to determine the at least one memory device fault condition. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2A Prong 2: Identification of Additional Elements
A memory device for connecting with a host in a system, the memory device comprising: an array of memory cells; (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
and a memory controller configured for controlling access to the array of memory cells, (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
the memory controller being configured to perform one or more memory device functions that enable the host to perform system operations, (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a generic computer. (MPEG 2106.05(f)) The computer is cited at such a high level of generality that it cannot be determined to be a particular machine (MPEP 2106.05(b)) and is simply linking the judicial exception to a particular technology (MPEP 2106.05(h))
Regarding Claim 2,
Step 2A Prong 1: Identification of Abstract Ideas
The memory device of claim 1, wherein the at least one safety mechanism monitor is configured to force a failure in performing at least one of the one or more memory device functions for the at least one safety mechanism (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and configured to determine the at least one safety mechanism fault condition based on whether the at least one safety mechanism detected the forced failure. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claim 4,
Step 2A Prong 1: Identification of Abstract Ideas
The memory device of claim 1, wherein the at least one safety mechanism monitor determines the at least one safety mechanism fault condition intermittently. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claim 5,
Step 2A Prong 1: Identification of Abstract Ideas
The memory device of claim 4, wherein the at least one safety mechanism fault condition is determined during times when the system is neither booting up nor performing normal system operations that are enabled by the one or more memory device functions. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claim 6,
Step 2A Prong 1: Identification of Abstract Ideas
The memory device of claim 1, wherein the at least one safety mechanism monitor is configured to store the at least one safety mechanism fault condition in nonvolatile memory for access by the host to assess whether the at least one safety mechanism is reliable. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claim 8,
Step 2A Prong 1: Identification of Abstract Ideas
The memory device of claim 1, further comprising using an alert system and status flags for the at least one safety mechanism to react to the at least one memory device fault condition, (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and using the alert system and the status flags for the at least one safety mechanism monitor to demonstrate coverage. (MPEP 2106.04(d)I, “Merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f)” are limitations that did not integrate a judicial exception into a practical application)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claim 12,
Step 2A Prong 1: Identification of Abstract Ideas
wherein the method comprises: performing one or more memory device functions, using the memory controller, that enable a host to perform system operations; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
determining at least one memory device fault condition using at least one safety mechanism in the memory controller, wherein the at last one memory device fault condition has a potential to adversely affect performance of at least one of the one or more memory device functions; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and determining at least one safety mechanism fault condition using at least one safety mechanism monitor in the memory controller, wherein the at least one safety mechanism fault condition can adversely affect an ability of the at least one safety mechanism to determine the at least one memory device fault condition, (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
wherein the host is configured to assess whether the at least one safety mechanism is reliable based on the at least one safety mechanism fault condition (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and is configured to assess whether the memory controller is reliable to perform the one or more memory device functions that enable the host to perform the system operations. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2A Prong 2: Identification of Additional Elements
A method performed using a host and a memory device that includes an array of memory cells and a memory controller configured for controlling access to the array of memory cells, (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a generic computer. (MPEG 2106.05(f)) The computer is cited at such a high level of generality that it cannot be determined to be a particular machine (MPEP 2106.05(b)) and is simply linking the judicial exception to a particular technology (MPEP 2106.05(h))
Regarding Claim 13,
Step 2A Prong 1: Identification of Abstract Ideas
The method of claim 12, further comprising: forcing a failure, using the at least one safety mechanism monitor, in performing at least one of the one or more memory device functions; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
using the at least one safety mechanism to determine the at least one memory device fault condition when the failure is forced; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
and using the at least one safety mechanism monitor to determine the at least one safety mechanism fault condition based on whether the at least one safety mechanism detected the failure. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2B: Significantly More Analysis
Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Regarding Claims 15-17 and 19,
The method of claims 15-17 and 19 performs the same method steps as the device of claims 4-6 and 8, and claims 15-17 and 19 are therefore rejected using the same rationale set forth above in the rejection of claims 4-6 and 8
Regarding Claim 20,
Step 2A Prong 2: Identification of Additional Elements
The method of claim 12, wherein the system operations include operations for an automotive system, and the memory device includes Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC) storage, or a solid state drive (SSD). (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a generic computer. (MPEG 2106.05(f)) The computer is cited at such a high level of generality that it cannot be determined to be a particular machine (MPEP 2106.05(b)) and is simply linking the judicial exception to a particular technology (MPEP 2106.05(h))
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by ANEJA (US 20240227825 A1)
Regarding Claim 1, ANEJA teaches:
A memory device for connecting with a host in a system (ANEJA, Fig. 2, 200, [0018] Safety and automotive SoCs may launch and execute such BISTs at system power-down, system power-up, or complete execution of all tests in a combination of at system power-up and system power-down.), the memory device comprising: an array of memory cells; (ANEJA, [0033] A single SOC may also include any number of general purpose and/or specialized processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash, etc.))
and a memory controller configured for controlling access to the array of memory cells, (ANEJA, Fig. 2, 210)
the memory controller being configured to perform one or more memory device functions that enable the host to perform system operations, (ANEJA, [0053] In certain aspects, the test module 348 may be integrated with another component, such as the processors 204, power management controller 208, memory controller 210, sensor controller 212, and/or driver assistance controller. [0052] The test module 348 may perform tests on any of various software components or modules, such as testing certain software applications (ADAS applications), algorithms (e.g., common calculations), other software components (e.g., device drivers, operating system, etc.) as well for ensuring correct operation. )
wherein the memory controller includes: at least one safety mechanism configured to determine at least one memory device fault condition that has a potential to adversely affect performance of at least one of the one or more memory device functions, (ANEJA, [0052] The test module 348 may perform tests on any of various software components or modules, such as testing certain software applications (ADAS applications), algorithms (e.g., common calculations), other software components (e.g., device drivers, operating system, etc.) as well for ensuring correct operation.)
and at least one safety mechanism monitor configured to determine at least one safety mechanism fault condition that has a potential to adversely affect an ability of the at least one safety mechanism to determine the at least one memory device fault condition. (ANEJA, [0052] The test module 348 may perform test(s) that verify the operational integrity of the BISTs, for example, via fault injection into the BISTs. For example, the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
Regarding Claim 2, ANEJA teaches:
The memory device of claim 1, wherein the at least one safety mechanism monitor is configured to force a failure in performing at least one of the one or more memory device functions for the at least one safety mechanism (ANEJA, [0052] The test module 348 may perform test(s) that verify the operational integrity of the BISTs, for example, via fault injection into the BISTs.)
and configured to determine the at least one safety mechanism fault condition based on whether the at least one safety mechanism detected the forced failure. (ANEJA, [0052] the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
Regarding Claim 4, ANEJA teaches:
The memory device of claim 1, wherein the at least one safety mechanism monitor determines the at least one safety mechanism fault condition intermittently. (ANEJA, [0055] The ECU 300a may perform test(s) (e.g., a BIST for logic, memory, and/or other electrical components) opportunistically at certain occasions when the vehicle is in a specific testing state. As an example, the testing state may include when the vehicle is not in use, when the vehicle is stationary (or immobile or parked), when the vehicle is powering down (shutting off or transitioning to a suspended state in response to a key-off action), when the vehicle is in an off state, when the vehicle is being refueled or re-charged, or at a certain time of day (e.g., at certain times when the vehicle is immobile like at night parked at home or during the day parked at work).)
Regarding Claim 5, ANEJA teaches:
The memory device of claim 4, wherein the at least one safety mechanism fault condition is determined during times when the system is neither booting up nor performing normal system operations that are enabled by the one or more memory device functions. (ANEJA, [0055] . As an example, the testing state may include when the vehicle is not in use...when the vehicle is powering down (shutting off or transitioning to a suspended state in response to a key-off action), when the vehicle is in an off state...)
Regarding Claim 6, ANEJA teaches:
The memory device of claim 1, wherein the at least one safety mechanism monitor is configured to store the at least one safety mechanism fault condition in nonvolatile memory for access by the host to assess whether the at least one safety mechanism is reliable. (ANEJA, [0058] ...the ECU 300a may store the test results (e.g., a BIST pass or fail) in non-volatile memory (e.g., the memory 220) or provide the test results to the other ECU(s) 300b. )
Regarding Claim 8, ANEJA teaches:
The memory device of claim 1, further comprising using an alert system and status flags for the at least one safety mechanism to react to the at least one memory device fault condition, (ANEJA, [0059] In certain cases, when a fault is detected, the ECU 300a (and/or the other ECU(s) 300b) may notify an entity of the fault, for example, where the entity may be the OEM or a vehicle care service. [0058] The ECU 300a may save the BIST status (e.g., pass or fail) and detailed BIST test results in memory for the ECU 300a to retrieve during context restore (e.g., during the next power on cycle of the ECU 300a)
and using the alert system and the status flags for the at least one safety mechanism monitor to demonstrate coverage. (ANEJA, [0058] the ECU 300a may check the test results to ensure the absence of any faults (such as a transient or permanent fault detected by the BIST tests [0059] As an example, upon detection of a permanent fault, the ECU 300a (and/or the other ECU(s) 300b) may inform the OEM via a wireless communication network (e.g., cellular communication). The OEM may launch and perform remote safety diagnostics for any potential recovery procedures. The OEM may perform remote diagnostics for possible recovery procedures.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 9-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ANEJA (US 20240227825 A1), in view of Johnson (US 20250007799 A1)
Regarding Claim 3, ANEJA does not explicitly teach:
The memory device of claim 2, wherein the memory controller is configured to reset the at least one memory device fault condition in response a reset signal received from the host after the failure is forced.
However, Johnson teaches:
The memory device of claim 2, wherein the memory controller is configured to reset the at least one memory device fault condition in response a reset signal received from the host after the failure is forced. (Johnson, [0049] . For example, Monitor library API 310 may inject the specified values in a payload and transmit the augmented payload to aggregator 206 having the specified values. The specified values may cause certain expected behaviors to occur downstream within the edge devices diagnostics system, and fault injection using the specified values at the monitor can test whether the expected behaviors would indeed occur. In some cases, monitor library API 310 may accept a request to reset an error/fault/occurrence counter. Monitor library API 310 may reset the counter to zero or some other specified value, if applicable.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine ANEJA with reset based upon request as taught by Johnson, because after a fault injection, which can be beneficial for testing whether the edge devices diagnostics system is working properly or as intended. Monitor library API may allow requestors to request configuration of a monitor to be modified and/or be reset back to default values. (Johnson, [0045])
Regarding Claim 9, ANEJA in view of Johnson teaches:
A system, comprising: a host configured to perform system operations within an automotive system configured to provide assisted driving functions or autonomous driving functions; (ANEJA, abstract, aspects of the present disclosure provide techniques and apparatus for testing a mixed safety system, such as system included in a vehicle)
and a memory device including an array of memory cells and a memory controller configured for controlling access to the array of memory cells, (ANEJA, Fig. 2, 210)
the memory controller being configured to perform one or more memory device functions that enable the host to perform the system operations, (ANEJA, [0053] In certain aspects, the test module 348 may be integrated with another component, such as the processors 204, power management controller 208, memory controller 210, sensor controller 212, and/or driver assistance controller. [0052] The test module 348 may perform tests on any of various software components or modules, such as testing certain software applications (ADAS applications), algorithms (e.g., common calculations), other software components (e.g., device drivers, operating system, etc.) as well for ensuring correct operation. )
wherein the memory controller includes: at least one safety mechanism configured to determine at least one memory device fault condition that has a potential to adversely affect performance of at least one of the one or more memory device functions, (ANEJA, [0052] The test module 348 may perform tests on any of various software components or modules, such as testing certain software applications (ADAS applications), algorithms (e.g., common calculations), other software components (e.g., device drivers, operating system, etc.) as well for ensuring correct operation.)
and at least one safety mechanism monitor configured to determine at least one safety mechanism fault condition that has a potential to adversely affect an ability of the at least one safety mechanism to determine the at least one memory device fault condition, (ANEJA, [0052] The test module 348 may perform test(s) that verify the operational integrity of the BISTs, for example, via fault injection into the BISTs. For example, the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
wherein the at least one safety mechanism monitor is configured to force a failure in performing at least one of the one or more memory device functions for the at least one safety mechanism (ANEJA, [0052] The test module 348 may perform test(s) that verify the operational integrity of the BISTs, for example, via fault injection into the BISTs.)
and configured to determine the at least one safety mechanism fault condition based on whether the at least one safety mechanism detected the forced failure, (ANEJA, [0052] the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
wherein the host is configured to assess whether the at least one safety mechanism is reliable based on the at least one safety mechanism fault condition (ANEJA, [0058] ...the ECU 300a may store the test results (e.g., a BIST pass or fail) in non-volatile memory (e.g., the memory 220) or provide the test results to the other ECU(s) 300b...Subsequently, on a next key-on (power-on) cycle, the ECU 300a may check the test results to ensure the absence of any faults (such as a transient or permanent fault detected by the BIST tests). )
and is further configured to assess whether the memory controller is reliable to perform the one or more memory device functions that enable the host to perform the system operations, (Johnson, [0045] the monitor library API 310 can allow for fault injection, which can be beneficial for testing whether the edge devices diagnostics system is working properly or as intended)
and wherein the memory controller is configured to reset the at least one memory device fault condition in response a reset signal received from the host. (Johnson, [0049] . For example, Monitor library API 310 may inject the specified values in a payload and transmit the augmented payload to aggregator 206 having the specified values. The specified values may cause certain expected behaviors to occur downstream within the edge devices diagnostics system, and fault injection using the specified values at the monitor can test whether the expected behaviors would indeed occur. In some cases, monitor library API 310 may accept a request to reset an error/fault/occurrence counter. Monitor library API 310 may reset the counter to zero or some other specified value, if applicable.)
Regarding Claim 10, ANEJA in view of Johnson teaches:
The system of claim 9, wherein the at least one safety mechanism fault condition is intermittently determined during a key off event. (ANEJA, [0055] The ECU 300a may perform test(s) (e.g., a BIST for logic, memory, and/or other electrical components) opportunistically at certain occasions when the vehicle is in a specific testing state. As an example, the testing state may include when the vehicle is not in use, when the vehicle is stationary (or immobile or parked), when the vehicle is powering down (shutting off or transitioning to a suspended state in response to a key-off action), when the vehicle is in an off state, when the vehicle is being refueled or re-charged, or at a certain time of day (e.g., at certain times when the vehicle is immobile like at night parked at home or during the day parked at work).)
Regarding Claim 11, ANEJA in view of Johnson teaches:
The system of claim 9, wherein the automotive system includes an Automotive Safety Integrity Level (ASIL) risk classification system, (ANEJA, [0018] Measures to detect such faults are designed in line with a particular automotive safety integrity level (ASIL), for example, as per functional safety standard, such as ISO 26262 as provided by the International Organization for Standardization (ISO).)
and the memory device includes Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC) storage, or a solid state drive (SSD). (ANEJA, [0084] For example, the ECU may operate in the suspended state, where the suspended state includes a suspend-to-memory (e.g., random access memory (RAM) or other types of memory such as non-volatile memory, universal flash storage, an embedded multi-media-card (eMMC), PCIe, Ethernet based storage drive, etc.) state.)
Regarding Claim 12,
The method of claim 12 performs the same method steps as the system of claim 9, and claim 12 is therefore rejected using the same rationale set forth above in the rejection of claim 9
Regarding Claim 13, ANEJA in view of Johnson teaches:
The method of claim 12, further comprising: forcing a failure, using the at least one safety mechanism monitor, in performing at least one of the one or more memory device functions; (ANEJA, [0052] The test module 348 may perform test(s) that verify the operational integrity of the BISTs, for example, via fault injection into the BISTs.)
using the at least one safety mechanism to determine the at least one memory device fault condition when the failure is forced; (ANEJA, [0052] the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
and using the at least one safety mechanism monitor to determine the at least one safety mechanism fault condition based on whether the at least one safety mechanism detected the failure. (ANEJA, [0052] the test module 348 may perform a test that confirms that a BIST is operating correctly by injecting a known failure and/or a known success into the BIST and verifying that a failure or a success is output or reported)
Regarding Claim 14,
The method of claim 14 performs the same method steps as the device of claim 3, and claim 14 is therefore rejected using the same rationale set forth above in the rejection of claim 3
Regarding Claim 15, ANEJA in view of Johnson teaches:
The method of claim 12, wherein the at least one safety mechanism fault condition is intermittently determined. (ANEJA, [0055] The ECU 300a may perform test(s) (e.g., a BIST for logic, memory, and/or other electrical components) opportunistically at certain occasions when the vehicle is in a specific testing state. As an example, the testing state may include when the vehicle is not in use, when the vehicle is stationary (or immobile or parked), when the vehicle is powering down (shutting off or transitioning to a suspended state in response to a key-off action), when the vehicle is in an off state, when the vehicle is being refueled or re-charged, or at a certain time of day (e.g., at certain times when the vehicle is immobile like at night parked at home or during the day parked at work).)
Regarding Claim 16, ANEJA in view of Johnson teaches:
The method of claim 15, wherein the at least one safety mechanism fault condition is determined during times when the system is neither booting up nor performing normal system operations that are enabled by the one or more memory device functions. (ANEJA, [0055] . As an example, the testing state may include when the vehicle is not in use...when the vehicle is powering down (shutting off or transitioning to a suspended state in response to a key-off action), when the vehicle is in an off state...)
Regarding Claim 17, ANEJA in view of Johnson teaches:
The method of claim 12, further comprising storing the at least one safety mechanism fault condition in nonvolatile for access by the host to assess whether the at least one safety mechanism is reliable. (ANEJA, [0058] ...the ECU 300a may store the test results (e.g., a BIST pass or fail) in non-volatile memory (e.g., the memory 220) or provide the test results to the other ECU(s) 300b. )
Regarding Claim 19, ANEJA in view of Johnson teaches:
The method of claim 12, further comprising using an alert system and status flags for the at least one safety mechanism to react to the at least one memory device fault condition, and using the alert system and the status flags for the at least one safety mechanism monitor to demonstrate coverage. (ANEJA, [0059] In certain cases, when a fault is detected, the ECU 300a (and/or the other ECU(s) 300b) may notify an entity of the fault, for example, where the entity may be the OEM or a vehicle care service. [0058] The ECU 300a may save the BIST status (e.g., pass or fail) and detailed BIST test results in memory for the ECU 300a to retrieve during context restore (e.g., during the next power on cycle of the ECU 300a)
Regarding Claim 20, ANEJA in view of Johnson teaches:
The method of claim 12, wherein the system operations include operations for an automotive system, and the memory device includes Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC) storage, or a solid state drive (SSD). (ANEJA, [0018] Measures to detect such faults are designed in line with a particular automotive safety integrity level (ASIL), for example, as per functional safety standard, such as ISO 26262 as provided by the International Organization for Standardization (ISO). [0084] For example, the ECU may operate in the suspended state, where the suspended state includes a suspend-to-memory (e.g., random access memory (RAM) or other types of memory such as non-volatile memory, universal flash storage, an embedded multi-media-card (eMMC), PCIe, Ethernet based storage drive, etc.) state.)
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over ANEJA (US 20240227825 A1), in view of Sassara (US 20210200620 A1)
Regarding Claim 7, ANEJA does not explicitly teach:
The memory device of claim 1, wherein the at least one safety mechanism is configured to react to the at least one memory device fault condition using a reaction path that includes at least one of firmware interrupts or a hardware path,
and the at least one safety mechanism monitor is configured to use the reaction path to demonstrate coverage for the reaction path.
However, Sassara teaches:
The memory device of claim 1, wherein the at least one safety mechanism is configured to react to the at least one memory device fault condition using a reaction path that includes at least one of firmware interrupts or a hardware path, (Sassara, abstract, In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. [0023] A real-time trigger can be signaled to firmware of the memory device through a hardware interrupt handled by an interrupt service routine (ISR). The ISR of the real-time trigger can invoke or resume a dedicated task, which is a real-time trigger task, in charge of dumping the device system status that can be in the form of an error log. )
and the at least one safety mechanism monitor is configured to use the reaction path to demonstrate coverage for the reaction path. (Sassara, abstract, In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine ANEJA with triggering hardware interrupt as taught by Sassara, which can be used to notify the device to timely capture all needed information in the device's error log and dump the error log to save the information for later failure analysis. (Sassara, [0019])
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ANEJA (US 20240227825 A1), in view of Johnson (US 20250007799 A1) and Sassara (US 20210200620 A1)
Regarding Claim 18, ANEJA in view of Johnson and Sassara teaches:
The method of claim 12, further comprising using a reaction path that includes at least one of firmware interrupts or a hardware path for the at least one safety mechanism to react to the at least one memory device fault condition, and using the reaction path for the at least one safety mechanism monitor to demonstrate coverage for the reaction path. (Sassara, abstract, In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. [0023] A real-time trigger can be signaled to firmware of the memory device through a hardware interrupt handled by an interrupt service routine (ISR). The ISR of the real-time trigger can invoke or resume a dedicated task, which is a real-time trigger task, in charge of dumping the device system status that can be in the form of an error log. )
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wilson (US 20210357299 A1): A method of testing a data storage system includes maintaining libraries of test routines, a first library including a set of normal-functional tests each operable to test corresponding normal functionality of the data storage system, a second library including a set of fault inserters each being independently operable to induce a corresponding fault condition into the data storage system. Normal-functional tests are executed concurrently with one or more of the fault inserters to cause the normal-functional tests to encounter the corresponding fault conditions during execution and thereby test a response of the normal functionality of the data storage system to the occurrence of the fault conditions.
LADKANI (US 20210294763 A1): A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.
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/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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