Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application No. 63635721 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Specification
The disclosure is objected to because of the following informalities: In paragraph [0070], line.
Appropriate correction is required.
Claim Objections
Claim 11, 12, 19, and 20 objected to because of the following informalities:
In claim 11, line 2-3, acronyms were introduced as a part of the claim. To ensure the scope of the invention, expansion of the acronyms is suggested.
In claim 12, line 2, “a set of memory components” seems to refer to the element introduced in claim 1, line 2 (“a set of memory components”). However, this could be interpreted as an introduction of new element that is not the element cited prior, which could cause indefinite scope.
In claim 19, line 5, “a debugging component” seems to refer to the element introduced in claim 19, line 3 (“a debugging component”). However, this could be interpreted as an introduction of new element that is not the element cited prior, which could cause indefinite scope.
In claim 20, line 7, “a debugging component” seems to refer to the element introduced in claim 20, line 5 (“a debugging component”). However, this could be interpreted as an introduction of new element that is not the element cited prior, which could cause indefinite scope.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-11, 13, 14, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Mendes et al. (US 20210357125 A1), hereinafter Mendes .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As per claim 1, Mendes teaches a system comprising:
a memory sub-system comprising a set of memory components (“memory sub-system that includes one or more components, such as memory devices” Paragraph [0013]);
a debugging component (Debug port Address Manager 113 in Fig. 1 and 2, and Slave Addr (Debug) 246 in Fig. 2) that is in a locked state by default (“In one embodiment, host system 120 sends a vendor specific command to memory sub-system 110 to request that debug slave address 246 be enabled (e.g., initialized)” Paragraph [0039]; under broadest reasonable interpretation, this is considered that the debugging component in a locked state by default); and
a processing device, operatively coupled to the set of memory components and the debugging component (“For example, the memory sub-system controller 115 can include a processor 117 (processing device)” Paragraph [0035]), and configured to perform operations comprising:
receiving, from a host over a first bus, authentication information associated with unlocking the debugging component (“At operation 710, the processing logic receives a privilege key from host system 120. Depending on the embodiment, the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216 to receive a request for debug information directed to the debug slave address 246, received with some other message, or received separately from any other message.” Paragraph [0061]; and Operation 604 of Fig. 6); and
in response to successfully authenticating the host based on the authentication information, unlocking the debugging component, the debugging component performing operations comprising (“the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216” Paragraph [0061]):
receiving one or more debug commands from the host via a second bus (“At operation 725, the processing logic receives, from host system 120, a request for debug information directed to debug slave address 246.” Paragraph [0063]; The request for debug information is considered equivalent to the debug command of the claimed invention); and
transmitting, to the host via the second bus, debugging information in response to receiving the one or more debug commands (“At operation 750, the processing logic sends the debug information to host system 120 over SMBus 124 coupled to SMBus port 216 of the memory sub-system 110.” Paragraph [0065]).
As per claim 2, Mendes teaches the debugging information includes a state of the memory sub-system representing a status of at least one of one or more data structures, one or more queues, or one or more state machines (“transfer debugging information, such as system state information” Paragraph [0015]).
As per claim 3, Mendes teaches the debugging component performs operations comprising:
receiving additional authentication information from the host via the second bus (“At operation 610, host system 120 sends a connection request to memory sub-system 110, […] In one embodiment, this connection request optionally includes the privilege key previously received from memory sub-system 110.” Paragraph [0056]); and
processing the one or more debug commands in response to successfully authenticating the host based on the additional authentication information (“If the connection request included the privilege key, memory sub-system 110 can further authenticate the privilege key” Paragraph [0056]).
As per claim 5, Mendes teaches the first bus comprises a system management bus (SMBus) (“data transferred from the memory sub-system to an associated host system over a system management bus (SMBus).” Paragraph [0016]) and the second bus comprises a peripheral component interconnect express (PCIe) bus (“The communication pipe can be implemented using any one of various technologies, and can include, for example, a peripheral component interconnect express (PCIe) bus,” Paragraph [0015]).
As per claim 6, Mendes teaches the debugging component comprises a universal asynchronous receiver-transmitter (UART) device (“Other conventional systems can transfer the debugging information using a universal asynchronous receiver-transmitter (UART) bus to a debugging system” Paragraph [0015]).
As per claim 7, Mendes teaches the authentication information comprises a key (“the host system can be provided with a privilege key to be included with any requests for debugging information” Paragraph [0016]; while Mendes’s disclosure did not explicitly mention the key being 256-bit, Mendes did not limit the key size either. Under broadest reasonable interpretation, this is considered to include 256-bit key), and
wherein the processing device successfully authenticates the host by comparing the authentication information with a known value (“In one embodiment, this connection request optionally includes the privilege key previously received from memory sub-system 110” Paragraph [0056]; this indicates the privilege key is being compared to known value from the debugging component’s side as debugging component provided the key to the host.).
As per claim 8, Mendes teaches the one or more debug commands comprise instructions to install debug firmware, the debugging component causing the processing device to boot using the debug firmware instead of default firmware, the debug firmware configured to generate different types of debugging information than the default firmware (“the host system can issue firmware or hardware debug print events (i.e., requests to pull debugging information) to the memory sub-system” Paragraph [0014]).
As per claim 9, Mendes teaches the memory sub-system is installed in an automotive environment and is associated with at least one of an infotainment system of the automotive environment or advanced driver assistance systems (ADAS) of the automotive environment (“The computing system 100 can be a computing device such as a […] a vehicle (e.g., airplane, drone, train, automobile” Paragraph [0020]; memory sub-system is part of computer system 100. See Fig. 1).
As per claim 10, Mendes teaches the one or more debug commands are provided to the debugging component without physically detaching the memory sub-system from the host (“The host system 120 can be coupled to the memory sub-system 110 via a physical host interface 122.” Paragraph [0023] and “In one embodiment, the memory sub-system 110 includes a debug port address manager component 113 that coordinates the transfer of debugging information from memory sub-system 110 to host system 120 over a communication pipe separate from PCIe bus 122.” Paragraph [0034]).
As per claim 11, Mendes teaches the debugging information comprises at least one of NVMe logs, or FailureAnalysisDump/VendorSpecific logs (“The host system 120 can further utilize an NVM Express (NVMe) interface” Paragraph [0023] and “In one embodiment, host system 120 sends a vendor specific command” paragraph [0038]).
(While Mendes does not directly teach the debugging information comprising SMART logs or SMART extended logs, the claim 11 recites “at least one of” listed subject matters. Some of the listed matters were disclosed by Mendes)
As per claim 13, Mendes teaches the authentication information is received in response to occurrence of a critical event of the memory sub-system (“In another embodiment, the memory sub-system can periodically, or in response to the occurrence of an event, provide the debugging information to the host system” Paragraph [0016] and “debug port address manager 113 […] can identify a subset of the available debug information based on a context of the request (e.g., severity of an event entry in the debug information” Paragraph [0041]).
As per claim 14, Mendes teaches the critical event comprises at least one of PCIe link drops, firmware asserts, command timeouts, entering of a write protect state in the memory sub-system, a loop of resets, and a threshold number of interrupts being transmitted by the processing device to the host (“An event, as used herein, generally refers to a detectable action performed by hardware, software, firmware, or a combination of any of the above in the memory sub-system. Some examples of an event include a memory sub-system controller sending and/or receiving data or accessing a memory location of a memory device, a warning related to some reliability statistic (e.g., raw bit error rate (RBER)) of a memory device, an error experienced by the memory sub-system controller in reading data from or writing data to a memory device, etc.” Paragraph [0014]).
As per claim 19, Mendes teaches a method comprising:
receiving, by a processing device from a host over a first bus, authentication information associated with unlocking a debugging component (“At operation 710, the processing logic receives a privilege key from host system 120. Depending on the embodiment, the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216 to receive a request for debug information directed to the debug slave address 246, received with some other message, or received separately from any other message.” Paragraph [0061]; and Operation 604 of Fig. 6);
in response to successfully authenticating the host based on the authentication information, unlocking a debugging component by the processing device (“the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216” Paragraph [0061]);
receiving, by the debugging component, one or more debug commands from the host via a second bus (“At operation 725, the processing logic receives, from host system 120, a request for debug information directed to debug slave address 246.” Paragraph [0063]; The request for debug information is considered equivalent to the debug command of the claimed invention); and
transmitting, by the debugging component to the host via the second bus, debugging information in response to receiving the one or more debug commands (“At operation 750, the processing logic sends the debug information to host system 120 over SMBus 124 coupled to SMBus port 216 of the memory sub-system 110.” Paragraph [0065]).
As per claim 20, Mendes teaches A non-transitory computer-readable storage medium (Machine-Readable Medium 924 in Fig. 9; “the instructions 926 include instructions to implement functionality corresponding to the debug port address manager 113 of FIG. 1)” Paragraph [0071]) comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving, by a processing device from a host over a first bus, authentication information associated with unlocking a debugging component (“At operation 710, the processing logic receives a privilege key from host system 120. Depending on the embodiment, the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216 to receive a request for debug information directed to the debug slave address 246, received with some other message, or received separately from any other message.” Paragraph [0061]; and Operation 604 of Fig. 6);
in response to successfully authenticating the host based on the authentication information, unlocking a debugging component by the processing device (“the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216” Paragraph [0061]);
receiving, by the debugging component, one or more debug commands from the host via a second bus (“At operation 725, the processing logic receives, from host system 120, a request for debug information directed to debug slave address 246.” Paragraph [0063]; The request for debug information is considered equivalent to the debug command of the claimed invention); and
transmitting, by the debugging component to the host via the second bus, debugging information in response to receiving the one or more debug commands (“At operation 750, the processing logic sends the debug information to host system 120 over SMBus 124 coupled to SMBus port 216 of the memory sub-system 110.” Paragraph [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mendes in view of Schilder et al. (US 20180189493 A1), hereinafter Schilder.
As per claim 4, Mendes teaches the system of claim 3 as stated above (See 35 U.S.C. 102 rejection for claim 3 for further details). Mendes does not directly teach the “system of claim 3, wherein the additional authentication information comprises a single use password (SUP).”
However, Schilder, in an analogous art, teaches use of single use password as authentication method (“the test mode ports and features may be unlocked by, for example, a password. […] for example, if One-Time-Password mode” Schilder Paragraph [0096]; Under broadest reasonable interpretation, one-time-password in Schilder’s disclosure is considered as equivalent to single use password from the claimed invention).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the system with memory sub-system comprising debugging module that enabled by authentication information and have additional authentication disclosed by Mendes to use one-time password as additional authentication information as disclosed by Schilder.
Furthermore, one skilled in the art would have been motivated by Schilder to use single use password an authentication method as Schilder’s one time password was used to unlock the module for debugging (“The locking mechanism may be unlocked by writing a correct password […] via direct path from the Debug Port 101 interface” Schilder Paragraph [0111]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mendes in view of Nixon et al. (US 20140053036 A1), hereinafter Nixon.
As per claim 12, Mendes teaches the system of claim 1 as stated above (See 35 U.S.C. 102 rejection for claim 1 for further details). Mendes further teaches debug commands comprise the sanitize command to delete the information stored in the memory components (“For example, the requests can include a request to […] erase data from memory device 130, etc.” Paragraph [0050]). Mendes does not directly teach the one or more debug commands comprise one of a request to place the memory sub-system in a specific power state that prevents the memory sub-system from entering a low-power mode, a request to modify speed of the memory sub-system or clocking mode of the memory sub-system, or a request to restructure a namespace of the memory sub-system.
However, Nixon, in an analogous art, teaches debug command (“The DSM includes multiple storage elements that may be programmed with multiple parameter values associated with multiple contexts. Each context may correspond to a given one of multiple instruction sequences.” Nixon Paragraph [0009]) comprise one of a request to place the memory sub-system in a specific power state that prevents the memory sub-system from entering a low-power mode (Examples of instruction sequences include […] a power-performance state (p-state).” Nixon Paragraph [0009]), a request to modify speed of the memory sub-system or clocking mode of the memory sub-system (“Examples of the state or action parameters 424a-424f may include identifiers of one or more clocks” Nixon Paragraph [0048]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the debug command that comprise sanitize command disclosed by Mends to have debug command further comprise one of power-state or clocking mode as disclosed by Nixon.
Furthermore, one skilled in the art would have been motivated by Nixon as Nixon discloses the implementation of debug state machine (DSM) on memory controller and the processor core controlling memory sub-system (See DSM 114 and 136 in Nixon Fig. 1).
Claim(s) 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mendes in view of Lohse (Lohse. (1969). Data communications control procedures for the USA standard code for information interchange. Communications of the ACM., 12(3)), in further view of Hopkins (US 20140013145 A1).
As per claim 15, Mendes However, Lohse, in an analogous art, teaches receiving one or more start-of-packet indicators from the host associated with respective one or more packets (“SOH delimits the start of a message heading.” Lohse 4.1.1, Function 1, Page 168 and “STX delimits the start of a message text.” Lohse 4.1.2, Function 1 Page 168);
sending an acknowledgment after receiving each of the one or more packets (“ACK is transmitted by a Slave station as an affirmative reply.” Lohse 4.1.7, Function 1, Page 168);
receiving an end-of-transmission (EOT) indicator after the one or more packets are received (“EOT--End of Transmission Definition. A communication control character used to indicate the conclusion of a transmission” Lohse 4.4.4, Page 168); and
receiving an end-of-transmission block (ETB) indicator to switch the debugging component from operating as a receiver to operating as a transmitter (“ETB calls for a reply from the Slave station receiving the transmission block.” Lohse 4.1.5, Function 3, page 168).
(Lohse did not explicitly limit its technology to the debugging module in the memory sub-system, but opens up the application to all data communications between modules, therefore, Lohse’s disclosure is considered as a prior art; “to perform the communication functions neces- sary for (1) the Establishment and Termination of transmission between stations and (2) the Transfer of Messages between stations.” Lohse 1. Scope and Introduction, Page 166)
Both Mendes and Lohse do not directly teach “periodically sending a waiting-for-packets indicator.”
However, Hopkins, in an analogous art, teaches debug module asserting waiting-for-packet indicator (“the following describes an exemplary message interface signalling protocol suitable for use on the interface between a shared hub and debug unit […] The receiver asserts READY when it is ready to receive data.” Hopkins Paragraph [0081]-[0082]; See Fig. 5 for an example)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the system with memory sub-system comprising debugging module disclosed by Mendes to have debugging module perform receiving start of the packet indicator, sending acknowledgement, receiving EOT indicator, receiving ETB indicator, as disclosed by Lohse, and periodically sending waiting for packet indicator, as disclosed by Hopkins.
Furthermore, one skilled in the art would have been motivated by Lohse to implement stated indicators and acknowledgement to meet the needs of data communication links having different configuration (“This standard specifies a variety of data communication control procedures to meet the needs of data communication links having dif- ferent configurations or complexity.” Lohse 1. Scope and introduction, Page 168) and further motivated by Hopkins to implement waiting-for-packet indicator to indicate it is ready to receive (“the receiver is ready to receive data as indicated by the assertion of READY” Paragraph [0083]).
As per claim 16, Mendes, Lohse, and Hopkins, in combination, teach the system of claim 15 as stated above (See 35 U.S.C. 103 rejection for claim 15 for further details). Mendes further teaches the one or more debug commands are received as part of the one or more packets (“At operation 622, host system 120 sends a request for debug information” Mendes Paragraph [0058]), and
wherein the debugging information is transmitted after the debugging component switches to operating as the transmitter (“At operation 520, the processing logic sends debug information to host system 120” Mendes Paragraph [0054] and “In some embodiments, the method 500 is performed by debug port address manager 113 of FIG. 1” Mendes Paragraph [0051]).
Mendes does not teach the elements of claim 15 as stated above (See 35 U.S.C. 103 rejection for claim 15 for further details).
However, Lohse, in an analogous art, teaches receiving one or more start-of-packet indicators from the host associated with respective one or more packets (“SOH delimits the start of a message heading.” Lohse 4.1.1, Function 1, Page 168 and “STX delimits the start of a message text.” Lohse 4.1.2, Function 1 Page 168);
sending an acknowledgment after receiving each of the one or more packets (“ACK is transmitted by a Slave station as an affirmative reply.” Lohse 4.1.7, Function 1, Page 168);
receiving an end-of-transmission (EOT) indicator after the one or more packets are received (“EOT--End of Transmission Definition. A communication control character used to indicate the conclusion of a transmission” Lohse 4.4.4, Page 168); and
receiving an end-of-transmission block (ETB) indicator to switch the debugging component from operating as a receiver to operating as a transmitter (“ETB calls for a reply from the Slave station receiving the transmission block.” Lohse 4.1.5, Function 3, page 168).
(Lohse did not explicitly limit its technology to the debugging module in the memory sub-system, but opens up the application to all data communications between modules, therefore, Lohse’s disclosure is considered as a prior art; “to perform the communication functions neces- sary for (1) the Establishment and Termination of transmission between stations and (2) the Transfer of Messages between stations.” Lohse 1. Scope and Introduction, Page 166)
Both Mendes and Lohse do not directly teach “periodically sending a waiting-for-packets indicator.”
However, Hopkins, in an analogous art, teaches debug module asserting waiting-for-packet indicator (“the following describes an exemplary message interface signaling protocol suitable for use on the interface between a shared hub and debug unit […] The receiver asserts READY when it is ready to receive data.” Hopkins Paragraph [0081]-[0082]; See Fig. 5 for an example)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the system with memory sub-system comprising debugging module disclosed by Mendes to have debugging module perform receiving start of the packet indicator, sending acknowledgement, receiving EOT indicator, receiving ETB indicator, as disclosed by Lohse, and periodically sending waiting for packet indicator, as disclosed by Hopkins.
Furthermore, one skilled in the art would have been motivated by Lohse to implement stated indicators and acknowledgement to meet the needs of data communication links having different configuration (“This standard specifies a variety of data communication control procedures to meet the needs of data communication links having dif- ferent configurations or complexity.” Lohse 1. Scope and introduction, Page 168) and further motivated by Hopkins to implement waiting-for-packet indicator to indicate it is ready to receive (“the receiver is ready to receive data as indicated by the assertion of READY” Paragraph [0083]).
As per claim 17, Mendes, Lohse, and Hopkins, in combination, teach the system of claim 15 as stated above (See 35 U.S.C. 103 rejection for claim 15 for further details). Mendes further teaches the host switches from operating as the receiver to operating as the transmitter after the end of receiving data from the debugging component (See Mendes Fig. 3 and Fig. 6). Mendes does not teach “wherein the debugging component performs operations comprising: detecting an additional waiting-for-packet indicator received from the host; in response to detecting the additional waiting-for-packet indicator, transmitting a start-of-packet indicator associated with a debugging packet to the host; sending the EOT indicator after the debugging packet is transmitted; and transmitting the ETB indicator.”
However, Lohse, in an analogous art further teaches transmitting a start-of-packet indicator associated with a debugging packet to the host (“SOH delimits the start of a message heading.” Lohse 4.1.1, Function 1, Page 168 and “STX delimits the start of a message text.” Lohse 4.1.2, Function 1 Page 168);
sending the EOT indicator after the debugging packet is transmitted (“EOT--End of Transmission Definition. A communication control character used to indicate the conclusion of a transmission” Lohse 4.4.4, Page 168); and
transmitting the ETB indicator (“ETB calls for a reply from the Slave station receiving the transmission block.” Lohse 4.1.5, Function 3, page 168).
(Lohse did not explicitly limit its technology to the debugging module in the memory sub-system, but opens up the application to all data communications between modules, therefore, Lohse’s disclosure is considered as a prior art; “to perform the communication functions neces- sary for (1) the Establishment and Termination of transmission between stations and (2) the Transfer of Messages between stations.” Lohse 1. Scope and Introduction, Page 166)
Both Mendes and Lohse do not directly teach “detecting an additional waiting-for-packets indicator.”
However, Hopkins, in an analogous art, further teaches detecting an additional waiting-for-packet indicator from the host (“the following describes an exemplary message interface signaling protocol suitable for use on the interface between a shared hub and debug unit […] The receiver asserts READY when it is ready to receive data.” Hopkins Paragraph [0081]-[0082]; See Fig. 5 for an example).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the system with memory sub-system comprising debugging module and host switching host operating as receiver to operate as transmitter disclosed by Mendes to have debugging module perform transmitting start of the packet indicator, sending EOT indicator, transmitting ETB indicator, as disclosed by Lohse, and detecting waiting for packet indicator, as disclosed by Hopkins.
Furthermore, one skilled in the art would have been motivated by Lohse to implement stated indicators to meet the needs of data communication links having different configuration (“This standard specifies a variety of data communication control procedures to meet the needs of data communication links having dif- ferent configurations or complexity.” Lohse 1. Scope and introduction, Page 168) and further motivated by Hopkins to implement waiting-for-packet indicator to indicate it is ready to receive (“the receiver is ready to receive data as indicated by the assertion of READY” Paragraph [0083]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mendes in view of Hopkins (US 20140013145 A1).
As per claim 18, Mendes teaches the system of claim 1 as stated above (See 35 U.S.C. 102 rejection for claim 1 for further details). Mendes further indicates debugging component going back to locked states after the operations (“In one embodiment, additional requests for debug information can be received and the requested debug information can be provided to host system 120 via SMBus 124 as long as the debug slave address 246 remains enabled.” Mendes Paragraph [0040]). Mendes does not directly teach the debugging component returns to the locked state in response to receiving a lock command in the one or more debug commands.
However, Hopkins, in an analogous art, teaches debugging component returns to the locked state in response to receiving a lock command in the one or more debug commands (“the debug architecture on chip is in a lock down mode. This means that no communications from the debug controller, other than authentication communications” Hopkins Paragraph [0141] and “the access controller may send a message to the shared hub to implement locks on pathways emanating from the shared hub.” Hopkins Paragraph [0144]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of claimed invention to have modified the system with memory sub-system comprising debugging module disclosed by Mendes to return to locked state after receiving locked command, as disclosed by Hopkins.
Furthermore, one skilled in the art would have been motivated by Hopkins to implement lock command to return the debugging component to lock state for security purposes (“For security, it is useful for access to a debug architecture on chip by an entity external to the chip to be restricted.” Hopkins Paragraph [0138]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200003833 A1 teaches the debugging module implemented and coupled to memory system or device. The debugging module can be activated by receiving activation command from the host. The debugging module receives debug instructions (e.g., debug clock frequency, debug protocol, etc.) from the host.
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/J.J./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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