Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application filed April 9, 2025, claims 1-20 are presented for examination. Claims 1 and 20 are independent claims.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 202410525463.3 filed in China on April 28, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted April 9, 2025.
Information Disclosure Statement
The Applicant’s Information Disclosure Statement filed (April 9, 2025) has been received, entered into the record, and considered.
Drawings
The drawings filed April 9, 2025 are accepted by the examiner.
Abstract
The abstract filed April 9, 2025 is accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
8. Claims 1-19 in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “configured” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “configured” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the words “a shielding component configured to, the first shielding element is
configured to, the second electrode portion is configured to, the transmission transistor is a bias adjustment transistor configured to, the adjustment signal line is configured to, a bias
adjustment transistor configured to, the reset signal line is configured to ” in claims 1, 3, 4, 10 and 17 with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 4, 5, 9, 11, 12, 14, 15, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 20230337465 Al) in view of Song (US 20240242670 A1).
As to Claim 1:
Huang et al. discloses a display panel (Huang, see Abstract, where Huang discloses a display panel and a display device are disclosed. The display panel includes: a base substrate; a pixel unit, located on the base substrate, the pixel unit including a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element, the pixel circuit includes a driving transistor, and the driving transistor includes a gate electrode; a first gate signal line, connected to the gate electrode of the driving transistor; a constant voltage line, configured to provide a first constant voltage to the pixel circuit; and a shield electrode, connected to the constant
voltage line, wherein an orthographic projection of the first gate signal line on the base substrate falls within an orthographic projection of the shield electrode on the base substrate), comprising: a substrate (Huang, see base substrate BS in figure 1 and paragraph [0049], where Huang discloses that FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As illustrated in FIG. 1, the display panel includes a base substrate BS); a light-emitting element (Huang, see 100b in figure 2 and paragraph [0050], where Huang discloses that FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a base substrate. As illustrated in FIG. 2, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b) comprising a first electrode portion (Huang, see E1 in figure 6A and paragraph [0073], where Huang discloses that the light-emitting element 100b includes a first electrode El and a second
electrode E2, and a light-emitting function layer located between the first electrode El and the second electrode E2. For example, the first electrode El is an anode, and the second electrode E2 is a cathode), a light-emitting layer (Huang, see light-emitting function layer FL in figure 6E), and a second electrode portion (Huang, see E2 in figure 6A and paragraph [0073], where Huang discloses that the light-emitting element 100b includes a first electrode El and a second electrode E2, and a light-emitting function layer located between the first electrode El and the second electrode E2. For example, the first electrode El is an anode, and the second electrode E2 is a cathode); a pixel driver circuit (Huang, see pixel circuit 100a in figure 6A and paragraph [0073], where Huang discloses that FIG. 6A illustrates a pixel circuit of one pixel unit of the display panel. As illustrated in FIG. 6A, the pixel unit 100 includes the pixel circuit 100a) located at a side of the substrate (Huang, see base substrate BS and 100a in figure 3) and comprising a drive transistor (Huang, see driving transistor T1 in figure 6A and paragraph [0073], where Huang discloses that FIG. 6A illustrates a pixel circuit of one pixel unit of the display panel. As illustrated in FIG. 6A, the pixel unit 100 includes the pixel circuit 100a and the light-emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor Tl), a light-emitting control transistor (Huang, see T5 in figure 6A and paragraph [0073], where Huang discloses a second light-emitting control transistor), and a transmission transistor (Huang, see T2 in figure 6A and paragraph [0077], where Huang discloses that as illustrated in FIG. 6A, a gate electrode T20 of the data writing transistor T2 is connected to the gate line GT, a first electrode T21 of the data writing transistor T2 is connected to the data line DT, and a second electrode T22 of the data writing transistor T2 is connected to a first electrode T11 of the driving transistor Tl); a light-emitting control scanning signal line extending in a first direction (Huang, see EML in figure 6A and paragraph [0079], where Huang discloses that as illustrated in FIG. 6A, the display panel further includes the light-emitting control signal line
EML), connected to a gate (Huang, see gate T50 in light-emitting control transistor T5 in figure 6A) of the light-emitting control transistor (Huang, see light-emitting control transistor T5 in figure 6A), and comprising a first connection line (Huang, see T51 and T52 in figure 6A); a second connection line comprising a first end electrically connected to a first electrode of the drive transistor (Huang, see T11 in drive transistor T1 in figure 6A) and a second end electrically connected to a first electrode of the transmission transistor (Huang, see T11 in drive transistor T1 connected to T22 of transmission transistor T2 in figure 6A), wherein the light-emitting control transistor (Huang, see light-emitting transistor T5 in figure 6A) comprises a first electrode electrically connected to a second electrode of the drive transistor (Huang, see T51 of light-emitting transistor T5 connected to T12 of drive transistor T1 in figure 6A) and a second electrode electrically (Huang, see T52 of light-emitting transistor T5 connected to N4 which is connected to electrode E1 of light emitting element in figure 6A) connected to the first electrode portion of the light-emitting element (Huang, see N4 and E1 in figure 6A); and a shielding component configured to receive a direct current voltage signal (Huang, see Se/LY4 in figure 6B and paragraph [0087], where Huang discloses that referring to FIG. 6B and FIG. 6C, in order to stabilize the potentials on the gate signal portion PTl, the display panel provided by the embodiment of the present disclosure provides a shield electrode SE and a constant voltage line LO, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The
shield electrode SE is connected to the constant voltage line L0, so that the voltage on the shield electrode SE is stable and can play a shielding role to prevent the conductive line Ll from affecting the potentials on the gate signal portion PTl. The orthographic projection of the first gate signal line SLl on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS), wherein in a direction perpendicular to a plane of the substrate (Huang, see Se/LY4 in figure 6B and paragraph [0087], where Huang discloses that referring to FIG. 6B and FIG. 6C, in order to stabilize the potentials on the gate signal portion PTl, the display panel provided by the embodiment of the present disclosure provides a shield electrode SE and a constant voltage line LO, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shield electrode SE is connected to the constant voltage line L0, so that the voltage on the shield electrode SE is stable and can play a shielding role to prevent the conductive line Ll from affecting the potentials on the gate signal portion PTl. The orthographic projection of the first gate signal line SLl on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS).
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Huang differs from the claimed subject in that Huang does not explicitly disclose that the shielding component is located between the first connection line and the second connection line, and the shielding component, the first connection line, and the second connection line overlap with each other.
However in an analogous art, Song discloses that the shielding component (Song, see shielding component SHE in figure 8) is located between the first connection line (Song, see T5 in figure 8) and the second connection line (Song, see T1 in figure 8), and the shielding component, the first connection line, and the second connection line overlap with each other (Song, see overlapping in red square in figure 8 below).
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It would have been obvious to one of ordinary skill in the art to modify the invention of Huang with Song. One would be motivated to modify Huang by disclosing shielding component is located between the first connection line and the second connection line, and the shielding component, the first connection line, and the second connection line overlap with each other as taught by Song, and thereby improving shielding functions in a display and biometric authentication (Song, see paragraphs [0003] and [0009]).
As to Claim 2:
Huang in view of Song discloses the display panel according to claim 1, wherein the pixel driver circuit further comprises a storage capacitor (Song, see Cst in figure 8), the storage capacitor (Song, see Cst in figure 8) comprises a first plate (Song, see connection between Cst and DT in figure 6) and a second plate (Song, see Cst and ELVDD in figure 6), and the first plate is reused as a gate of the drive transistor (Song, see Cst and DT in figure 6); and in the direction perpendicular to the plane of the substrate (Song, see CE11 and SUB in figure 12), the first plate (Song, see CE11 in figure 12) is located between the substrate (Song, see SUB in figure 12) and the second plate (Song, see CE12 in figure 12); and wherein the shielding component comprises a first shielding element electrically connected to the second plate (Song, see SHE and CE12 in figure 8).
As to Claim 3:
Huang in view of Song discloses that the display panel according to claim 2, wherein the first shielding element is configured to receive a first supply voltage, and the second electrode portion is configured to receive a second supply voltage lower than the first supply voltage (Song, see paragraphs [0207] and [0096], where Song discloses that the shielding electrode SHE is connected (e.g., electrically connected) to the driving voltage line VDL, a driving voltage ELVDD of a certain level may be applied to the shielding electrode SHE. Voltage line VL may include a driving voltage line and a common voltage line. The driving voltage ELVDD may be a high potential voltage for driving light emitting elements and light sensing elements, and the common voltage ELVSS may be a low potential voltage for driving the light emitting elements and the light sensing elements. For example, the driving voltage ELVDD may have a higher potential than the common voltage ELVSS).
As to Claim 4:
Huang in view of Song discloses the display panel according to claim 2, wherein the transmission transistor is a data writing transistor configured to write a data signal into the gate of the drive transistor; or the transmission transistor is a bias adjustment transistor configured to write a bias adjustment voltage into the first electrode of the drive transistor (Huang, see paragraph [0019], where Huang discloses that pixel circuit further comprises a data writing transistor, a gate electrode of the data writing transistor is connected to the gate line, a first electrode of the data writing transistor is connected to the data line, and a second electrode of the data writing transistor is connected to a first electrode of the driving transistor).
As to Claim 5:
Huang in view of Song discloses that the display panel according to claim 2, wherein the first shielding element is disposed in a same layer as the second plate (Song, see SHE and CE12 in figure 8).
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As to Claim 9:
Huang in view of Song discloses that the display panel according to claim 1, further comprising an adjustment signal line (Song, see GWLk in figure 6) electrically connected to a second electrode of the transmission transistor (Song, see transmission transistor T1 in figure 6), wherein the shielding component comprises a second shielding element electrically connected to the adjustment signal line (Song, see G1 in T1 connected to SHE in figure 8).
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As to Claim 11:
Huang in view of Song discloses that the display panel according to claim 9, wherein the second shielding element is disposed in a same layer as the adjustment signal line (Song, see G1 in T1 connected to SHE in figure 8).
As to Claim 12:
Huang in view of Song discloses that the display panel according to claim 11, wherein a plurality of pixel driver circuits arranged in the first direction share a same second shielding element (Song, see all transistors (driving circuits) in green connected to shielding element SHE in figure 8).
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As to Claim 14:
Huang in view of Song discloses that the display panel according to claim 9, wherein the second shielding element is reused as the adjustment signal line (Song, see G1 in T1 connected to SHE in figure 8).
As to Claim 15:
Huang in view of Song discloses that the display panel according to claim 1, further comprising a reset signal line and a reset transistor, wherein the reset transistor comprises a first electrode electrically connected to a gate of the drive transistor or the first electrode portion of the light-emitting element, and a second electrode electrically connected to the reset signal line; and wherein the shielding component comprises a third shielding element electrically connected to the reset signal line (Song, see LT2 and SHE in figure 8 and paragraph [0158], where Song discloses that The kth reset control signal RSTk may be a signal transmitted to the kth reset control line RSTLk and a signal for controlling tum-on and turn-off of the second sensing transistor LT2).
As to Claim 18:
Huang in view of Song discloses that the display panel according to claim 15, wherein the second connection line is disposed in a same layer as the reset signal line (Song, see LT2 and SHE in figure 8 and paragraph [0158], where Song discloses that The kth reset control signal RSTk may be a signal transmitted to the kth reset control line RSTLk and a signal for controlling tum-on and turn-off of the second sensing transistor LT2).
As to Claim 20:
Huang et al. discloses a display device, comprising a display panel (Huang, see Abstract, where Huang discloses a display panel and a display device are disclosed. The display panel includes: a base substrate; a pixel unit, located on the base substrate, the pixel unit including a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element, the pixel circuit includes a driving transistor, and the driving transistor includes a gate electrode; a first gate signal line, connected to the gate electrode of the driving transistor; a constant voltage line, configured to provide a first constant voltage to the pixel circuit; and a shield electrode, connected to the constant voltage line, wherein an orthographic projection of the first gate signal line on the base substrate falls within an orthographic projection of the shield electrode on the base substrate) comprising: a substrate (Huang, see base substrate BS in figure 1 and paragraph [0049], where Huang discloses that FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As illustrated in FIG. 1, the display panel includes a base substrate BS); a light-emitting element (Huang, see 100b in figure 2 and paragraph [0050], where Huang discloses that FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a base substrate. As illustrated in FIG. 2, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b) comprising a first electrode portion (Huang, see E1 in figure 6A and paragraph [0073], where Huang discloses that the light-emitting element 100b includes a first electrode El and a second electrode E2, and a light-emitting function layer located between the first electrode El and the second electrode E2. For example, the first electrode El is an anode, and the second electrode E2 is a cathode), a light-emitting layer (Huang, see light-emitting function layer FL in figure 6E), and a second electrode portion (Huang, see E2 in figure 6A and paragraph [0073], where Huang discloses that the light-emitting element 100b includes a first electrode El and a second electrode E2, and a light-emitting function layer located between the first electrode El and the second electrode E2. For example, the first electrode El is an anode, and the second electrode E2 is a cathode); a pixel driver circuit (Huang, see pixel circuit 100a in figure 6A and paragraph [0073], where Huang discloses that FIG. 6A illustrates a pixel circuit of one pixel unit of the display panel. As illustrated in FIG. 6A, the pixel unit 100 includes the pixel circuit 100a) located at a side of the substrate (Huang, see base substrate BS and 100a in figure 3) and comprising a drive transistor (Huang, see driving transistor T1 in figure 6A and paragraph [0073], where Huang discloses that FIG. 6A illustrates a pixel circuit of one pixel unit of the display panel. As illustrated in FIG. 6A, the pixel unit 100 includes the pixel circuit 100a and the light-emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor Tl), a light-emitting control transistor (Huang, see T5 in figure 6A and paragraph [0073], where Huang discloses a second light-emitting control transistor), and a transmission transistor (Huang, see T2 in figure 6A and paragraph [0077], where Huang discloses that as illustrated in FIG. 6A, a gate electrode T20 of the data writing transistor T2 is connected to the gate line GT, a first electrode T21 of the data writing transistor T2 is connected to the data line DT, and a second electrode T22 of the data writing transistor T2 is connected to a first electrode T11 of the driving transistor Tl); a light-emitting control scanning signal line extending in a first direction (Huang, see EML in figure 6A and paragraph [0079], where Huang discloses that as illustrated in FIG. 6A, the display panel further includes the light-emitting control signal line EML), connected to a gate (Huang, see gate T50 in light-emitting control transistor T5 in figure 6A) of the light-emitting control transistor (Huang, see light-emitting control transistor T5 in figure 6A), and comprising a first connection line (Huang, see T51 and T52 in figure 6A); a second connection line comprising a first end electrically connected to a first electrode of the drive transistor (Huang, see T11 in drive transistor T1 in figure 6A) and a second end electrically connected to a first electrode of the transmission transistor (Huang, see T11 in drive transistor T1 connected to T22 of transmission transistor T2 in figure 6A), wherein the light-emitting control transistor (Huang, see light-emitting transistor T5 in figure 6A) comprises a first electrode electrically connected to a second electrode of the drive transistor (Huang, see T51 of light-emitting transistor T5 connected to T12 of drive transistor T1 in figure 6A) and a second electrode electrically (Huang, see T52 of light-emitting transistor T5 connected to N4 which is connected to electrode E1 of light emitting element in figure 6A) connected to the first electrode portion of the light-emitting element (Huang, see N4 and E1 in figure 6A); and a shielding component configured to receive a direct current voltage signal Huang, see Se/LY4 in figure 6B and paragraph [0087], where Huang discloses that referring to FIG. 6B and FIG. 6C, in order to stabilize the potentials on the gate signal portion PTl, the display panel provided by the embodiment of the present disclosure provides a shield electrode SE and a constant voltage line LO, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shield electrode SE is connected to the constant voltage line L0, so that the voltage on the shield electrode SE is stable and can play a shielding role to prevent the conductive line Ll from affecting the potentials on the gate signal portion PTl. The orthographic projection of the first gate signal line SLl on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS), wherein in a direction perpendicular to a plane of the substrate Huang, see Se/LY4 in figure 6B and paragraph [0087], where Huang discloses that referring to FIG. 6B and FIG. 6C, in order to stabilize the potentials on the gate signal portion PTl, the display panel provided by the embodiment of the present disclosure provides a shield electrode SE and a constant voltage line LO, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shield electrode SE is connected to the constant voltage line L0, so that the voltage on the shield electrode SE is stable and can play a shielding role to prevent the conductive line Ll from affecting the potentials on the gate signal portion PTl. The orthographic projection of the first gate signal line SLl on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS).
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Huang differs from the claimed subject in that Huang does not explicitly disclose that the shielding component is located between the first connection line and the second connection line, and the shielding component, the first connection line, and the second connection line overlap with each other.
However in an analogous art, Song discloses that the shielding component (Song, see shielding component SHE in figure 8) is located between the first connection line (Song, see T5 in figure 8) and the second connection line (Song, see T1 in figure 8), and the shielding component, the first connection line, and the second connection line overlap with each other (Song, see overlapping in red square in figure 8 below).
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It would have been obvious to one of ordinary skill in the art to modify the invention of Huang with Song. One would be motivated to modify Huang by disclosing shielding component is located between the first connection line and the second connection line, and the shielding component, the first connection line, and the second connection line overlap with each other as taught by Song, and thereby improving shielding functions in a display and biometric authentication (Song, see paragraphs [0003] and [0009]).
Allowable Subject Matter
Claims 6, 7, 8, 10, 13, 16 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 6, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the first shielding element comprises a first shielding sub-element, and in the direction perpendicular to the plane of the substrate, the first shielding sub-element overlaps with the first connection line and the second connection line; and wherein a width of the first shielding sub-element in a second direction is greater than a width of the first connection line in the second direction intersecting the first direction”.
Referring to claim 7 and dependent claims 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the pixel driver circuit further comprises a first reset transistor, the first reset transistor comprises a first electrode electrically connected to the first plate, an oxide semiconductor channel, and a top gate; and a film layer of the oxide semiconductor channel is located between a film layer of the second plate and a film layer of the top gate in the direction perpendicular to the plane of the substrate; and wherein the first shielding element is disposed in a same layer as the top gate”.
Referring to claim 10, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the adjustment signal line is configured to transmit a bias adjustment voltage; and the transmission transistor is a bias adjustment transistor configured to write the bias adjustment voltage into the first electrode of the drive transistor.”.
Referring to claim 13, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the adjustment signal line extends in the first direction; and wherein the display panel further comprises an auxiliary adjustment signal line extending in a second direction intersecting the first direction, and the auxiliary adjustment signal line is electrically connected to at least one of the adjustment signal line or the second shielding element by a through-hole”.
Referring to claim 16, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein a plurality of reset transistors are provided and comprise a first reset transistor and a second reset transistor, and a plurality of reset signal lines are provided and comprise a first reset signal line and a second reset signal line; wherein the first reset transistor comprises a first electrode electrically connected to the gate of the drive transistor and a second electrode electrically connected to the first reset signal line, and the second reset transistor comprises a first electrode electrically connected to the first electrode portion of the light-emitting element and a second electrode electrically connected to the second reset signal line; and wherein the third shielding element is electrically connected to at least one of the first reset signal line or the second reset signal line”.
Referring to claim 17, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the transmission transistor is a bias adjustment transistor configured to write a bias adjustment voltage into the first electrode of the drive transistor; and wherein the reset signal line is configured to transmit a reset voltage”.
Referring to claim 19, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “comprising a plurality of pixel sub-regions, wherein the reset signal line extends in a second direction intersecting the first direction, wherein in a same pixel sub-region, in the first direction, an orthographic projection of the second connection line onto the substrate and an orthographic projection of a channel of the drive transistor onto the substrate are respectively located at two sides of an orthographic projection of the reset signal line onto the substrate”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Han (US 12367815 B2) discloses a display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, and the light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located therebetween; the pixel circuit includes a driving transistor, and the first electrode of the light-emitting element is electrically connected to a first electrode of the driving transistor; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is adjacent to the second sub-pixel, and an orthographic projection of the first electrode of the light-emitting element of the first sub-pixel on the base substrate does not overlap an orthographic projection of the pixel circuit of the second sub-pixel on the base substrate. In still another embodiment, dynamic animation population for avatar control is described.
Contact Information
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/NELSON M ROSARIO/Primary Examiner, Art Unit 2624