DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-11, 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2022/0327999) in view of Xie et al. (US 2025/0273134).
As to Claim 8, Choi et al. discloses A display driver circuit for driving a display panel, the display panel comprising a full refresh display area (fig.1,3; display areas 110, 114 {read as full refresh display areas}) and a partial refresh display area (fig.1,3; display areas 108, 112 {read as partial refresh areas}), the display driver circuit comprising: a timing control circuit, configured to output a plurality of gate clock signals to the display panel, the plurality of gate clock signals being used by a gate driving circuit in the display panel, to generate a plurality of scan driving signals (fig.2-4, para.0040-0041, timing controller 206, generates gate clock signals GCLK being used by gate driver 210 to generate gate line signals G1-G4);
wherein in a partial refresh frame period, the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area.
Choi et al. discloses during a power save mode, a plurality of gate clock signals (fig.4, GCLK1, GCLK2) toggle during a periods corresponding to display areas 110, 114 (fig.4,5b) and the pixels in display areas 110, 114 are addressed (para.0050,0065-0068).
Choi et al. does not expressly disclose wherein in a partial refresh frame period, the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area.
Xie et al. discloses a display comprising full refresh display area (fig.8, display area A1 (read as full refresh area); para.0145) and partial refresh display area (fig.8, display area A2, A3; para.0145), wherein in a partial refresh frame period (fig.8, period A1), the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area (fig.8, scan signals corresponding to area A1 toggle and control signal SW1 remains at high level, during period A1, and area A1 is refreshed) and stop toggling during M horizontal line periods corresponding to the partial refresh display area (fig.8, scan signals do not toggle during periods A2,A3 corresponding to display areas A2,A3).
It would have been obvious to one of ordinary of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi et al. with the teachings of Xie et al., such that the gate clock signals (of Choi) corresponding to scan signals of full refresh display area (110,114 of Choi) toggle during a refresh period (of Xie) and does not toggle during the periods corresponding to the partial refresh areas (Xie). The motivation being to enable the display panel to have a partitioned multi-frequency display function.
As to Claim 9, Choi et al. in view of Xie et al. disclose wherein the plurality of gate clock signals keep toggling during a full refresh frame period, including N horizontal line periods corresponding to the full refresh display area and M horizontal line periods corresponding to the partial refresh display area (Choi-fig.4-5, gate clock signals; Xie-fig.9, scan signals and switch signal toggle during periods A1 corresponding to full refresh display area A1 and period A2 corresponding partial refresh display area A2).
As to Claim 10, Choi et al. in view of Xie et al. disclose wherein the timing control circuit is further configured to output a shift clock to a plurality of shift register circuits of the gate driving circuit (Choi-fig.4, para.0046-0048; timing controller outputs gate start pulses GSP to shift registers 310-340), and the plurality of shift register circuits are configured to generate a plurality of shift control signals according to the shift clock, wherein the plurality of shift control signals are used for sequentially outputting the plurality of scan driving signals (Choi-fig.4, para.0038, 0042, 0046-0048,0053,0057).
As to Claim 11, Choi et al. in view of Xie et al. disclose whrein the plurality of shift register circuits output the plurality of shift control signals in the M horizontal line periods corresponding to the partial refresh display area (Choi-para.0053-0055, shift control signals to areas 108 and 112 (partial refresh areas)).
As to Claim 13, Choi et al.in view of Xie et al. disclose a plurality of source driving channels (fig.2, column drivers 208), configured to stop outputting display data to the display panel in response to the plurality of gate clock signals stopping toggling (Choi-0037-0038; Xie-para.0149).
As to Claim 14, Choi et al. in view of Xie et al. disclose wherein the timing control circuit is further configured to stop outputting a plurality of switching signals to the display panel in response to the plurality of gate clock signals stopping toggling, wherein each of the plurality of switching signals is used to electrically connect one of a plurality of source driving channels of the display driver circuit and one of a plurality of data lines of the display panel (Choi-fig.4-5-ares 110,114 are addressed, areas 108,112 are not addressed; Xie-fig.8, 30, data voltage is not output to partial refresh area A2/A3; para.0130, 0149).
As to Claims 1-4, 6-7 are method claims drawn to the apparatus of Claims 8-11,13-14 and are rejected for the reasons as set forth above.
As to Claim 15, Choi et al. discloses A gate driving circuit of a display panel, the display panel comprising a full refresh display area and a partial refresh display area (fig.1,3; display areas 110, 114 {read as full refresh display areas}) and display areas 108, 112 {read as partial refresh areas}, the gate driving circuit comprising: a plurality of shift register circuits comprising a first shift register circuit and a second shift register circuit (fig.3, shift registers 310-340), wherein the first shift register circuit is configured to generate a first shift control signal which is utilized for generating a plurality of first scan driving signals driving scan lines in the full refresh display area (fig.3, shift register 320; para.0045-0050, as a result of GSP2 output to shift register 320, pixel rows in display area 110 are addressed), and the second shift register circuit is configured to generate a second shift control signal which is utilized for generating a plurality of second scan driving signals driving other scan lines in the partial refresh display area (fig.3, shift register 310, para.0045-0050; pixel rows in display area 108 are addressed in response to GSP1 output to shift register 310); and
a plurality of output enable circuits, comprising a first output enable circuit (fig.3, gate line drivers 210 in correspondence with shift registers 320/340) and a second output enable circuit (fig.3, gate line drivers 210 in correspondence with shift registers 310/330), wherein the first output enable circuit is configured to generate the plurality of first scan driving signals according to the first shift control signal and a plurality of gate clock signals (fig.3-4; para.0034, 0041,0043-0050, gate line driver 210 generate gate line signals based on output from shift register 320) , and
the second output enable circuit is configured to generate the plurality of second scan driving signals according to the second shift control signal and the plurality of gate clock signals (fig.3-4; para.0034, 0041,0043-0050, gate line driver 210 generate gate line signals based on output from shift register 310);
wherein the second output enable circuit (fig.3, gate driver 210-shift register 310/330) stops outputting the plurality of second scan driving signals in response to the plurality of gate clock signals stopping toggling (fig.3-4; para.0050, when signals GSP1 and GSP3 are not output to shift register 310/330, the pixel rows in display areas 108,112 are not addressed and remain off).
Choi et al. does not expressly disclose the plurality of gate clock signals stopping toggling.
Xie et al. discloses control signal SW1 remains at high level, and scan signals toggle, during period A1, in which display area A1 is refreshed and control signal SW1 remains low and scan signals stop toggling during periods A2/A3 in which display areas A2/A3 are not refreshed (fig.8).
It would have been obvious to one of ordinary of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi et al. with the teachings of Xie et al., such that the gate clock signals (of Choi) corresponding to scan signals of partial refresh areas (108,112) of Choi) stop toggling during the periods in which the display area is not being refreshed (as disclosed by Xie). The motivation being to enable the display panel to have a partitioned multi-frequency display function.
As to Claim 16, Choi et al. in view of Xie et al. disclose wherein the first output enable circuit outputs the plurality of first scan driving signals in response to the plurality of gate clock signals keeping toggling (Choi- fig.3-4; para.0034, 0041,0043-0050, gate line driver 210 generate gate line signals based on output from shift register 320 and control signals GSP,GCLK).
As to Claim 17, Choi et al. in view of Xie et al. disclose wherein the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area (Choi-fig.3-4, gate clock signals toggle during periods corresponding display areas 110/114 in which pixel rows of display areas 110/114 are addressed) and stop toggling during M horizontal line periods corresponding to the partial refresh display area (Choi-fig.3-4, gate clock signals toggle during periods corresponding display areas 108/110 in which pixel rows of display areas 108/110 are off; Xie-fig.8- control signals do not toggle during periods corresponding to display areas A2/A3).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2022/0327999) in view of Xie et al. (US 2025/0273134), further in view of Hwang (US 2023/0214037).
As to Claim 18, Choi et al. in view of Xie et al., do not expressly disclose, but Hwang discloses: wherein each of the plurality of output enable circuits comprises a plurality of logic gates, each logic gate for performing a logic operation on a received shift control signal and a gate clock signal among the plurality of gate clock signals to generate a scan driving signal (fig.9, para.0167-0172).
It would have been obvious to one of ordinary of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Choi et al in view of Xie et al., with the teachings of Hwang, the motivation being to generate the scan signal in synchronization with the gate clock.
Allowable Subject Matter
Claims 5, 12, 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “outputting a reset signal to a plurality of shift register circuits of the gate driving circuit, wherein in the partial refresh frame period, the reset signal comprises a first pulse before a frame start pulse and a second pulse after the plurality of gate clock signals stop toggling” in combination with the other limitations in the claim.
Claim 12 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the timing control circuit is further configured to output a reset signal to a plurality of shift register circuits of the gate driving circuit, wherein in the partial refresh frame period, the reset signal comprises a first pulse before a frame start pulse and a second pulse after the plurality of gate clock signals stop toggling” in combination with the other limitations in the claim.
Claim 19 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the plurality of shift register circuits are further configured to receive a reset signal, to stop outputting the plurality of shift control signals in the partial refresh display area” in combination with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627