DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/18/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-11, 13,14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2025/0166575) in view of Choi et al. (US 2022/0327999), further in view of Awakura et al. (US 2007/0291021).
As to Claim 8, Huang et al. discloses A display driver circuit for driving a display panel, the display panel comprising a full refresh display area (fig.3-7, display area AA) and a partial refresh display area (fig.3-4, para.0052; display area including only the lines that need to be partially refreshed), the display driver circuit comprising:
a timing control circuit (fig.3-7; timing sequence control circuit 11, time sequence gating circuit 12 ), configured to output a plurality of gate clock signals to the display panel, the plurality of gate clock signals being received by and used by a gate driving circuit in the display panel, to generate a plurality of scan driving signals (fig.3-7; para.0051-0053; scanning signals transmitted to gate lines 1-m based on frame start signal GSTV and gating signal LSEL);
wherein in a partial refresh frame period, the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area (fig.6, para.0049- LSEL is high gate lines 2 and gate lines 3 need to be partially refreshed, and low for gate lines 1 and gate line 4 that do not need to be refreshed; fig.8, 0064; in a second frame, LSEL is high for image 2 that is partially refreshed, and is low for image 1 does not need to be refreshed; in a third frame, LSEL high for image 3 that needs to be partially refreshed and low for image 1-image 2 that do not need to be refreshed; in a fourth frame, LSEL high for image 4 that needs to be partially refreshed and is low for images 1,3,2 that do not need to be refreshed).
Huang et al. does not expressly disclose where the timing control circuit output a plurality of gate clock signals to the display panel, the plurality of gate clock signals being received by and used by a gate driving circuit in the display panel; the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area
Choi et al. discloses timing control circuit output a plurality of gate clock signals to the display panel, the plurality of gate clock signals being received by and used by a gate driving circuit in the display panel (fig.2-4, para.0040-0041, 0042-0043; timing controller 206, generates gate clock signals GCLK being used by gate driver 210 to generate gate line signals G1-G4); the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area (fig.4, 5B; para.0032, 0059,0066-0068; in a power save mode, during period 504a- the clock signals GCLK keep toggling, during which areas 110,114 are addressed (partially refreshed) and period 504b-clock signals GCLK do not toggle, during which areas 108,112 are not driven).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang et al. with the teachings of Choi et al., by providing a plurality of gate clocks signals (GCLKs) (as disclosed by Choi) such that the gate clocks keep toggling when the selected gate lines or image need to be partially refreshed and do not toggle during the gate lines or image that do not need to be refreshed. The motivation being to provide a power save mode for a partial area display to reduce power consumption of the partial display and the effects of burn-in.
Huang et al. in view of Choi et al. do not expressly disclose horizontal periods. Awakura et al. discloses a horizontal clock signal including a plurality of line periods (fig.2B, horizontal synchronizing timing). Awakura further discloses wherein during a partial update operation a partial display timing signal (118) toggles during a plurality of horizontal line periods and dos not toggle during a plurality of horizontal line periods (para.0042, 0066).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Huang et al. in view of Choi et al., with the teachings of Awakura, such that the gate clock signals and gating signal (Huang, Choi) toggle for a number of horizontal line periods when an partial refresh for display area is needed and do not toggle for the display area where the refresh is not needed. The motivation being to avoid image distortion in partial display.
As to Claim 9, Huang et al. in view of Choi et al, as modified by Awakura et al, disclose wherein the plurality of gate clock signals keep toggling during a full refresh frame period, including N horizontal line periods corresponding to the full refresh display area and M horizontal line periods corresponding to the partial refresh display area (Huang-fig.8, LSEL signal is high during full refresh of image 1; Choi-fig.5B, fig.4, gate clock signals360).
As to Claim 10, Huang et al. in view of Choi et al, as modified by Awakura et al, disclose wherein the timing control circuit is further configured to output a shift clock to a plurality of shift register circuits of the gate driving circuit (Choi-para.0046-0048), and the plurality of shift register circuits are configured to generate a plurality of shift control signals according to the shift clock, wherein the plurality of shift control signals are used for sequentially outputting the plurality of scan driving signals (Choi-para.0042,0046-0048,0053,0057).
As to Claim 11, Huang et al. in view of Choi et al, as modified by Awakura et al, disclose wherein the plurality of shift register circuits output the plurality of shift control signals in the M horizontal line periods corresponding to the partial refresh display area (Choi-para.0042,0046-0048,0053,0057)
As to Claim 13, Huang et al. in view of Choi et al., as modified by Awakura et al. disclose, a plurality of source driving channels, configured to stop outputting display data to the display panel in response to the plurality of gate clock signals stopping toggling (Huang-fig.5, para.0050-generates data signal corresponding to the gating signal LSEL; Choi-fig.1,5, para.0034, 0037-0038, 0066-0067; during period 504b, gate clock signals are not toggling, and display areas are not addressed).
As to Claim 14, , Huang et al. in view of Choi et al., as modified by Awakura et al. disclose wherein the timing control circuit is further configured to stop outputting a plurality of switching signals to the display panel in response to the plurality of gate clock signals stopping toggling, wherein each of the plurality of switching signals is used to electrically connect one of a plurality of source driving channels of the display driver circuit and one of a plurality of data lines of the display panel (Huang-fig.5- 6, para.0048, when gating signal LSEL is low, scanning signal is not transmitted to the gate line and data is not supplied; Choi-fig.4-5, para.0066-0067, gate clock signals when do not toggle, display areas are not addressed)
As to Claims 1-4, 6-7 are method claims drawn to the apparatus of Claims 8-11,13-14 and are rejected for the reasons as set forth above.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2025/0166575) in view of Choi et al. (US 2022/0327999).
As to Claim 15, Huang et al. discloses A gate driving circuit of a display panel, the display panel comprising a full refresh display area and a partial refresh display area, the gate driving circuit comprising: a plurality of shift register circuits, comprising a first shift register circuit and a second shift register circuit (fig.5, para.0019, 0053,0059; shift register G1-Gm), wherein the first shift register circuit is configured to generate a first shift control signal which is utilized for generating a plurality of first scan driving signals driving scan lines in the full refresh display area (fig.4-8; para.0016, 0053, first shift register G1 receives start signal GSTV and shifts and outputs the scanning signal that is further input to an input end of the next shift register), and the second shift register circuit is configured to generate a second shift control signal which is utilized for generating a plurality of second scan driving signals driving other scan lines in the partial refresh display area (fig.4-8; para.0016, 0053, first shift register G1 receives start signal GSTV and shifts and outputs the scanning signal that is further input to an input end of the next shift register); and
a plurality of output enable circuits, comprising a first output enable circuit and a second output enable circuit and configured to receive a plurality of gate clock signals, (fig.4-8; time sequence switch circuits 1-m, receive gating signal LSEL),
wherein the first output enable circuit is configured to generate the plurality of first scan driving signals according to the first shift control signal and the plurality of gate clock signals (fig.4, switch 1 is connected to first shift register and first gate line 1 based on first shift register output and gating signal LSEL) and
the second output enable circuit is configured to generate the plurality of second scan driving signals according to the second shift control signal and the plurality of gate clock signals (fig.4, switch 2 is connected to second shift register and second gate line 2, based on second shift register output and gating signal LSEL);
wherein the second output enable circuit stops outputting the plurality of second scan driving signals in response to the plurality of gate clock signals stopping toggling (fig.6, switch does not output scanning signal when the gating signal is low)
Huang et al. does not expressly disclose the first shift register circuit is configured to generate a first shift control signal which is utilized for generating a plurality of first scan driving signals driving scan lines in the full refresh display area, and the second shift register circuit is configured to generate a second shift control signal which is utilized for generating a plurality of second scan driving signals driving other scan lines in the partial refresh display area; wherein the first output enable circuit is configured to generate the plurality of first scan driving signals according to the first shift control signal and the plurality of gate clock signals and the second output enable circuit is configured to generate the plurality of second scan driving signals according to the second shift control signal and the plurality of gate clock signals; wherein the second output enable circuit stops outputting the plurality of second scan driving signals in response to the plurality of gate clock signals stopping toggling
Choi et al. discloses a first shift register circuit is configured to generate a first shift control signal which is utilized for generating a plurality of first scan driving signals driving scan lines in the full refresh display area (fig.3-4, shift register 310 addresses a plurality of pixel rows of display area 108 via gate line drivers 210; para.0032, 0043, 0046-0048), and the second shift register circuit is configured to generate a second shift control signal which is utilized for generating a plurality of second scan driving signals driving other scan lines in the partial refresh display area (fig.3-4, shift register 320 addresses a plurality of pixel rows of display area 110 via gate line drivers 210; para.0043, 0046-0048); wherein the first output enable circuit is configured to generate the plurality of first scan driving signals according to the first shift control signal and the plurality of gate clock signals (fig.3-4, para.0041,0043,0046-0048; gate drivers 210 corresponding to shift register 310 generate gate signals based on gate start signals GSP 1 and gate clock signals 360) and the second output enable circuit is configured to generate the plurality of second scan driving signals according to the second shift control signal and the plurality of gate clock signals (fig.3-4, para.0041,0043,0046-0048; gate drivers 210 corresponding to shift register 320 generate gate signals based on gate start signals GSP2 and gate clock signals 360); wherein the second output enable circuit stops outputting the plurality of second scan driving signals in response to the plurality of gate clock signals stopping toggling (fig.3-5B, para.0049-0056, 0066-0067, gate clock GCLK do not toggle during period 504b during which display areas are not addressed).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang et al. with the teachings of Choi et al, the motivation being to provide a power save mode for a partial area display to reduce power consumption of the partial display and the effects of burn-in.
As to Claim 16, Huang et al. in view of Choi et al. disclose wherein the first output enable circuit outputs the plurality of first scan driving signals in response to the plurality of gate clock signals keeping toggling (Huang-fig.4-6, switch m output scan signal in response to gating signal LSEL; Choi-fig.3-5b, para.0032,0034,0041,0043-0050; gate line driver 210 generates gate line signals based on output from shift register and gate clock signal, where the gate clock signals toggle during the display area being addressed).
Claim 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2025/0166575) in view of Choi et al. (US 2022/0327999), further in view of Awakura et al. (US 2007/0291021).
As to Claim 17, Huang et al. in view of Choi et al. disclose wherein the plurality of gate clock signals keep toggling during N horizontal line periods corresponding to the full refresh display area and stop toggling during M horizontal line periods corresponding to the partial refresh display area (Huang-fig.5-6, 8 gating select signal LSEL is high during full refresh of image 1; fig.4, 5B; para.0032, 0059,0066-0068; in a power save mode, during period 504a- the clock signals GCLK keep toggling, during which areas 110,114 are addressed (partially refreshed) and period 504b-clock signals GCLK do not toggle, during which areas 108,112 are not driven).
Huang et al. in view of Choi et al. do not expressly disclose horizontal periods. Awakura et al. discloses a horizontal clock signal including a plurality of line periods (fig.2B, horizontal synchronizing timing). Awakura further discloses wherein during a partial update operation a partial display timing signal (118) toggles during a plurality of horizontal line periods and dos not toggle during a plurality of horizontal line periods (para.0042, 0066).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Huang et al. in view of Choi et al., with the teachings of Awakura, such that the gate clock signals and the gating signal (Huang, Choi) toggle for a number of horizontal line periods when an partial refresh for display area is needed and do not toggle for the display area where the refresh is not needed. The motivation being to avoid image distortion in partial display.
Claim 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2025/0166575) in view of Choi et al. (US 2022/0327999), further in view of Hwang (US 2023/0214037).
As to Claim 18, Huang et al. in view of Choi et al. do not expressly disclose but Hwang disclose: wherein each of the plurality of enable circuit circuits comprises a plurality of logic gates, each logic gate for performing a logic operation on a received shift control signal and a gate clock signal among the plurality of gate clock signals to generate a scan driving signal (fig.9, para.0167-0172).
It would have been obvious to one of ordinary of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Huang et al. in view of Choi et al., with the teachings of Hwang, the motivation being to generate the scan signal in synchronization with the gate clock.
Allowable Subject Matter
Claims 5, 12, 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 5, 12, 19 are allowable over the prior art of record for the reasons noted in OA 02/12/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,8,15 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO892 form.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
Prosecution Insights