Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This is the initial Office Action based on the application filed on April 10, 2025. The Examiner acknowledges the following:
3. Claims 1 – 16 were filed.
4. The specification was amended and replaced with a clean copy on the same date as to include paragraph numbers and to be in appropriate format.
5. The drawings filed on 04/10/2025 are accepted by the Examiner.
6. Current claims 1 – 16 are pending. And they are being considered for examination.
Information Disclosure Statement
7. The IDS documents filed on filed on 04/10/2025, 07/14/2025 and 07/30/2025 are acknowledged by the Examiner.
Priority
8. Priority data is based on a Japanese patent application JP-2024-065613, filed on 04/15/2024. Certified copies of the documents were filed to the office on 05/24/2025.
Claim Rejection under 35 U.S.C. 112(b)
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Claim 8:
Claims 8 recites “The device according to claim 1, wherein a W/L ratio indicating a ratio of a channel width W and a channel length L of the first amplification transistor is lower than a W/L ratio of the second amplification transistor”.
Claim 8 depends on claim 1 and there is no “channel” indicated there that could provide an indication for what Applicant means for “channel width W” or “channel length L” – What Applicant means for the limitation “channel”? The re is no way one can make use of the instant application as for this limitation.
Claim 1 is rejected under 35 U.S.C. 112(b) because there is no antecedent basis for its limitations; besides, the claim language is confusing and misleading and it is not clear what the inventor(s) is/are pursuing as their invention.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7, 9 and 12 – 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Hiromu Kato et al., WO-2023/048235 A1, hereinafter Kato”. (Note: Kato is art is from the IDS document. The WO art is used for its publication date and US 2024/0373143 A1 is used as the translation of the WO publication. The paragraphs and drawings cited below referred to the US publication).
Regarding Claim 1 – 16:
Kato teaches a solid-state imaging element comprising: a pixel circuit that outputs a pixel signal as an input signal and, in a case where a rolling shutter mode to start exposure sequentially row by row is selected, outputs the pixel signal as a first output signal; a sample-hold circuit that holds the input signal and outputs the input signal as a second output signal in a case where a global shutter mode to start exposure simultaneously for all pixels is selected; and a changeover switch that selects any one of the first and second output signals and outputs the selected one to an analog-to-digital converter, further comprising: a current supply switch that connects a first vertical signal line to a predetermined power supply voltage in the case where the global shutter mode is selected and that connects the first vertical signal line to the changeover switch in the case where the rolling shutter mode is selected, wherein the pixel circuit outputs the first output signal via the first vertical signal line, and the sample-hold circuit outputs the second output signal via a second vertical signal line, wherein the pixel circuit includes first and second photoelectric converting elements, a first transfer transistor that transfers a charge from the first photoelectric converting element to a floating diffusion layer, a second transfer transistor that transfers a charge from the second photoelectric converting element to the floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit, and a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal, wherein the pixel circuit includes a photoelectric converting element, a transfer transistor that transfers a charge from the photoelectric converting element to a floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit, and a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal and, further comprising: a vertical scanning circuit that supplies a predetermined clip level to a gate of the selection transistor when the global shutter mode is selected and a predetermined reset level is held at the sample-hold circuit.
Regarding Claim 1:
Kato teaches,
A photoelectric conversion device (Fig 1 and Fig 2, imaging device 100. See [0083; 0088]) that comprises a pixel array including
a plurality of pixels (Fig 2, the solid-sate pixel element or array 200 includes a pixel array section 220 with a plurality of pixels. See [0088]) arranged to form a plurality of rows and a plurality of columns, and
a read circuit including a plurality of column circuits (Fig 2, column signal processing circuit 260, wherein the column signal processor 260 receives the load MOS circuit 250 (See [0092 – 0094]) and then it performs AD conversion process or CDS processing for each column via the ADC 261 (See Fig 4; [0116; 0117])])configured to read signals from the pixel array, wherein
each pixel includes a photoelectric converter (Fig 3, photodiode 311. See [0096; 0097]) configured to accumulate charges corresponding to incident light, a charge-voltage converter (Fig 3, FD 314. See [0096 ]), a transporter configured to transport charges from the photoelectric converter to the charge- voltage converter (Fig 3, transfer transistor 312. See [0096; 0097]),
a first amplification transistor configured to amplify a voltage of the charge-voltage converter (Fig 3, upstream amplification transistor 315 corresponds to the first amplification transistor. See [0096; 0098; 0099]), a first current source configured to supply a first current to the first amplification transistor (Fig 3, current source transistor 316 supplies the current to the upstream amplification transistor 315. See [0096; 0099]),
a storage configured to hold an output of the first amplification transistor (Fig 3, capacitors 321 and 322 and selecting circuit may be used to hold the level of the FD region 314 during the p-phase and the D-phase. See [0100; 0101; 0102; 0107; 0110; 0111]), and a second amplification transistor configured to amplify a voltage supplied from the storage (Fig 3, downstream circuit 350 includes a downstream amplification transistor 351, which amplifies the level of the downstream node 340. See [0103]),
each column circuit includes a second current source configured to supply a second current to the second amplification transistor (Fig 2 and Fig 4, in the load MOS circuit block 250, a vertical signal line 309. In addition, each of the vertical signal lines 309 is connected with a load MOS transistor 251 that supplies a predetermined current id2. See [0116]), and
the first current is smaller than the second current (In Fig 5, the vertical scanning circuit 211 controls the current source transistors 316 of all the rows (all the pixels) to supply the current id1. Here, id1_[n] in the figure represents currents of pixels in the n-th row. Since an IR drop increases when a current id becomes a large current, the current id1 needs to be in the order of several nano-amperes (nA) to several dozen nano-amperes (nA). On the other hand, the load MOS transistors 251 in all the columns are in the OFF state, and the current id2 is not supplied to the vertical signal lines 309 (See [0125]). However, nothing in Kato precludes to have both currents on and one to be larger than the other, as in a case with id2 be on and id1 be off, then any value of id2 would be larger than id1. See [0125]).
Regarding Claim 2:
The rejection of claim 1 is incorporated herein. As for claim 2 limitations, Kato Figs 2 and 5. teach that when the exposure control in which exposure is started and ended simultaneously for all the pixels as described above is called a global shutter scheme. With this exposure control, the upstream circuit 310 of each of all the pixels sequentially generates a reset level and a signal level. The reset level is held at the capacitive element 321, and the signal level is held at the capacitive element 322 (See 0110]). Fig 5 shows a timing chart depicting an example of a global shutter operation in the first embodiment of the present technology. From timing T0 immediately before the start of exposure to timing T1 after a lapse of a pulse period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst and transfer signal trg to all the rows (i.e., all the pixels). As a result, all the pixels are PD-reset, and exposure is started simultaneously in all the rows. Fig 5, the write operation, wherein the reset levels are sampled-and-hold after time T2 and the signal levels are sampled and held after time T4, and wherein the time period between exposure start time T1 and T4 is referred as exposure period, which means that the write operation duration is the same as for all pixels as it is when operating the global shutter mode (See [0119 – 0125]).
Regarding Claims 4 and 5:
The rejection of claim 1 is incorporated herein. As for claims 4 and 5 limitations, Kato Fig 11, teaches an example of an operation of the solid-state imaging element 200.
The vertical scanning circuit 211 performs exposure of all the pixels (step S901), sequentially selecting rows and at the end of the exposure of each row, the reading out of the row is started. A global shutter mode reads out all rows after the exposure of all pixels is completed (See [0146 – 0148]). Fig 41 is a timing chart depicting an example of an operation of the solid-state imaging element in the rolling shutter mode in the eighth embodiment of the present technology. As illustrated in the figure, the vertical scanning circuit 211 (not depicted) sequentially selects rows, and causes exposure to be started for the selected rows (See [0287]).
Regarding Claim 7:
The rejection of claim 1 is incorporated herein. As for claim 7 limitations, Kato teaches that under the control of the vertical scanning circuit 211, the current source transistor 316 supplies a current id1 (See [0099]) and the load MOS transistor 251 that supplies a predetermined current id2 (See [0116]). Controlling the current of a transistor through the gate-source voltage of the upstream amplification transistors 315 (See [0123]).
Regarding Claim 9:
The rejection of claim 1 is incorporated herein. The limitations of claim 9 does not provide allowable subject matter. Additionally, nothing in Kato precludes that the area one amplification transistor be smaller or larger than the other
Regarding Claims 12 and 15:
The rejection of claim 1 is incorporated herein. As for claim 12 limitations, Kato Fig 17 shows an example of stacked structure of the imaging device 200 with a first layer or upper pixel chip 201 which includes the pixel array 221; the lower pixel array section 220 is arranged on the lower layer 202; the column signal processing 260, the vertical scanning circuit 211, the timing control circuit 212, the DAC 233 and the load MOS circuit 250 are arranged on the circuit layer 203 (See [0170 – 0173]).
As for claim 15 and as seen in Fig 17, the plurality of pixels are arranged in two substrates as in Fig 15 (See [0163 – 0166])or in three substrates as seen in Fig 17 (See [0170 – 0173]).
Regarding Claim 13:
The rejection of claim 1 is incorporated herein. As for claim 13 limitations, Kato teaches in Figs 3 and 4 that the second amplification transistor (or the downstream amplification transistor 351) is connected to the vertical signal line 309, wherein the vertical signal line 309 corresponds to a pixel column (See [0116]).
Regarding Claim 14:
The rejection of claims 1 and 13 is incorporated herein. As for claim 14 limitations, Kato teaches in Fig 3 an example of the pixel 300, wherein the selecting circuit 330 includes a selection transistor 332. The downstream circuit 350 includes a downstream amplification transistor 352 (See [0101; 0103]).
Regarding Claim 16:
The rejection of claim 1 is incorporated herein. As for claim 16, Kato Fig 1, imaging device 100 with imaging element 200, image control section 130 and recording section 120, wherein imaging element 200 provides a signal 209 to be processed by the recording section 120 (See [0083; 0084]).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over “Hiromu Kato et al., WO-2023/048235 A1, hereinafter Kato”, in view of “ Xinqiao Liu, US 2019/0052788 A1, hereinafter Liu”. (Note: Kato is art is from the IDS document. The WO art is used for its publication date and US 2024/0373143 A1 is used as the translation of the WO publication. The paragraphs and drawings cited below referred to the US publication. Liu is art from the IDS as well).
Regarding Claim 3:
The rejection of claim 1 is incorporated herein. Kato teaches Figs 2 and 5. that when the exposure control in which exposure is started and ended simultaneously for all the pixels as described above is called a global shutter scheme. With this exposure control, the upstream circuit 310 of each of all the pixels sequentially generates a reset level and a signal level. The reset level is held at the capacitive element 321, and the signal level is held at the capacitive element 322 (See 0110]). Fig 3, upstream amplification transistor 315 corresponds to the first amplification transistor. See [0096; 0098; 0099]. As for the storage Fig 3, capacitors 321 and 322 and selecting circuit may be used to hold the level of the FD region 314 during the p-phase and the D-phase (See [0100; 0101; 0102; 0107; 0110; 0111]). Fig 45, Kato teaches pixel blocks 302 with 4 pixels adjacent to each other (See [0301}); however, it fails to teach the pixels divided into. Liu teaches a plurality of blocks, which in the same field of endeavor is taught by Liu. Liu teaches that photo arrays that use global signals to control the exposure time, therefore, have the same exposure time regardless of the lighting conditions (See [0005; 0006]). Fig 3 shows the pixels divided into a plurality of pixel blocks 310, wherein each pixel block 310 contains 4 rows and 4 columns, resulting in 16 total pixels (See [0036; 0037]).
Therefore, by modifying Kato with the arrays as taught by Liu, it would make possible to use varied of exposure times and to adjust the exposure time of each block (See Liu [0006]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over “Hiromu Kato et al., WO-2023/048235 A1, hereinafter Kato”, in view of Herb Huang et al., US 2008/0129911 A1, hereinafter Huang”.
Note: the rejection under 35 U.S.C. 112b is being taken into account on the rejection below.
Regarding Claim 8:
The rejection of claim 1 is incorporated herein. Kato teaches claim 1. As for claim 8 limitations, it is interpreted that Applicant is claiming the area or size of a pixel switch circuit, which probably includes a MOSFET transistor and a capacitor, that is not mentioned on Kato; however, it is taught by Huang. As for that matter, Huang teaches that in the LCD technology, each pixel switch circuit includes a MOSFET transistor and a capacitor (See [0004; 0005]) and according to his invention it is possible to increase the design area of a switch circuit and switch circuits with high performance may be designed and the flexibility of the design may be increased as well (See [0024]). Fig 2A shows a pixel switch circuit layer 22 including a metal-oxide-semiconductor field-affect transistor MOSFT, which is formed on a silicon substrate 21 (See [0031]). When a voltage is applied on a gate of the MOSFET of the pixel switch circuit layer 22, the MOSFET is turned on, and since the upper electrode of the capacitor is electrically connected with the source of the MOSFET, the capacitor is charged via the voltage applied on the signal pad 203 (See [0045]).
By adding a pixel switch circuit to Kato, it is possible to increase the design area that would increase the W/L ratio and the gate area, then providing a higher performance (See Huang [0024]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over “Hiromu Kato et al., WO-2023/048235 A1, hereinafter Kato”, in view of “Y. Kumagai et al., WO-2023/048235 A1, hereinafter Kumagai”. (Note: Kumagai is art is from the IDS document. The WO art is used for its publication date and US 2025/0126375 A1 is used as the translation of the WO publication. The paragraphs and drawings cited below referred to the US publication).
Regarding Claims 10 and 11:
The rejection of claim 1 is incorporated herein. Kato teaches claim 1; however, it is silent about the limitations of claims 10 and 11, which in the same field of endeavor is taught by Kumagai. Kumagai, Fig 2 shows the constant current circuit 105 connecting two MOS transistors 108 and 109 in series (See [0120; 0121; 0122]).
By modifying Kato with the teachings of Kumagai, the noise can be reduced by connecting the two MOS transistors in series and supplying different bias voltages to the respective gates. Further, it is possible to reduce the fluctuation of the output current when the power supply voltage fluctuates (See Kumagai [0122]).
Note: As for cascode transistors: See Wakashima US 2021/0067721 A1, Fig 2 and paragraph [0034], wherein the constant current 112 comprises a constant current transistor CS 211, a cascode transistor CAS 212 and a current source switch CSEN 213
Allowable Subject matter
12. Claim 6 is objected because its dependence to a base rejected claim; however, they would be allowed if written in an independent form.
Conclusion
13. The prior art is made of record and not relied upon is considered pertinent to applicant’s disclosure.
1. H. Sekine et al., US 12,317,611 B2 - it includes the same assignee and different inventor(s). It teaches a photoelectric conversion element provided in a semiconductor layer having first and second surfaces includes a first region of a first conductivity type, a second region of a second conductivity type closer to the second surface than the first region and forming a p-n junction with the first region, a third region of the first conductivity type closer to the second surface than the second region, a fourth region of the second conductivity type closer to the second surface than the third region, a fifth region of the second conductivity type between the third fourth regions, and a sixth region of the second conductivity type surrounding a region where the first, second, third, and fifth regions are disposed in a plan view. The fifth region has an area smaller than that of the third region in the plan view, and overlaps with the first region in the plan view.
2. S. Wakashima, US 2021/0067721 A1 – it includes the same assignee and a different inventor. It teaches an image capturing apparatus including a pixel array, an AD converter, an output line configured to connect the pixel and the AD converter, a reset unit configured to reset the output line, an amplification transistor configured to amplify a signal from the pixel, a connection unit configured to connect a source of the amplification transistor to the output line, a constant current source, and a control unit configured to, after a voltage of the output line is reset, cause a constant current to flow to the output line and to control to connect a source of the amplification transistor to the output line, wherein the control unit sets a value of the constant current so that the constant current is a lower value than a current required to drive the output line.
Contact
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY S.B. CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on M-F 8:00-5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARLY S CAMARGO/Primary Examiner, Art Unit 2638
Prosecution Insights