DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Duty of Disclosure
Applicant is reminded of 37 C.F.R. 1.56(a-b) which states:
(a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclose information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclose all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by §§ 1.97 (b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:
(1) Prior art cited in search reports of a foreign patent office in a counterpart application, and
(2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.
(b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made of record in the application, and
(1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or
(2) It refutes, or is inconsistent with, a position the applicant takes in:
(i) Opposing an argument of unpatentability relied on by the Office, or
(ii) Asserting an argument of patentability.
(3) A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 5, 7, 9, and 12-15 include the term “coupled”. This term is used with different meanings in patents in this field. In some, the term means directed linked through a low impedance path such as a wire. In others, the term includes both directed linked through a low impedance path, such as a wire or via, and indirectly linked through low impedance paths, such as wires, and one or more electrical devices or components, such as a transistor. It is unclear which meaning is intended in this application.
For most of the coupled elements in the claims, the circuit diagrams in the figures show them directly linked. However, the circuit diagrams do not show the pass transistors directly linked to the power supply line. The circuit diagrams in the figures use the notation of a dot at the intersection of two lines to indicate that those lines are electrically connected, while the absence of a dot indicates that those lines are not electrically connected. Figures 5 and 8 do not show T1-T8 directly linked to PWL1 or PWL2. Similarly, figures 6 and 7 do not show T1-T4 directly linked to PWL. It is unclear whether Applicant intended a direct link that is just not shown or whether Applicant only intended an indirect link.
Thus, claims 1-3, 5, 7, 9, and 12-15 are indefinite based on the use of the term “coupled”. Claims 4, 6, 8, 10, and 11 are rejected based on their dependence on claim 1 or 5. For purposes of obviousness, the term “coupled” will be interpreted as only covering the directly linked interpretation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9, 10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2022/0262730) in view of Asenov et al. (US 11,894,049) and Weste et al. (CMOS VLSI Design).
In regards to claim 1, Liaw teaches a static random access memory device (“a static random-access memory (SRAM)”, paragraph 0004) comprising:
at least one word line (WL, figure 2);
a first bit line and a second bit line (BL and BLB, figure 2);
a power supply line (VDD, figure 2);
a first ground line (1st VSS, figure 2) and a second ground line (2nd Vss, figure 2), wherein the power supply line runs in a direction parallel to the first bit line, the second bit line (Figure 6B shows these running in the Y direction), the first ground line, and the second ground line (See figure 6D), and the power supply line runs in a direction perpendicular to the at least one word line (See figure 6C); and
a static random access memory cell (“an SRAM cell”, paragraph 0005) including:
a first inverter and a second inverter cross-coupled and coupled to the power supply line, wherein the first inverter is coupled to the first ground line, and the second inverter is coupled to the second ground line (Figure 2 shows cross-coupled inverters formed by PU-1 and PD-1 and PU-2 and PD-2, PU-1 and PU-2 are both coupled to VDD, PD-1 is coupled to 1st Vss, and PD-2 is connected to 2nd Vss);
a first pass transistor coupled to the at least one word line, the first bit line, and the first inverter (See PG-1 in figure 2); and
a second pass transistor coupled to the at least one word line, the second bit line, and the second inverter (See PG-2 in figure 2).
Liaw fails to teach the first pass transistor coupled to the power supply line; and
the second pass transistor coupled to the power supply line.
Asenov teaches using a first pMOS pass transistor and a second pMOS pass transistor (abstract and figure 3) which “can achieve: 1) improvements in writability; 2) improvements in readability while maintaining stability; and 3) flip the polarity of the bit line pre-charge from ‘1’ to ‘0’, which can prove beneficial when the pMOS pass gate is stronger than the nMOS pass gate” (Col. 3, lines 29-34). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov such that the first pass transistor is a pMOS pass transistor and the second pass transistor is a pMOS pass transistor which “can achieve: 1) improvements in writability; 2) improvements in readability while maintaining stability; and 3) flip the polarity of the bit line pre-charge from ‘1’ to ‘0’, which can prove beneficial when the pMOS pass gate is stronger than the nMOS pass gate” (id.).
Liaw in view of Asenov fails to teach that the first pMOS pass transistor coupled to the power supply line; and
the second pMOS pass transistor coupled to the power supply line.
Weste teaches that the first pMOS pass transistor coupled to the power supply line (“For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage.”, page 8, paragraph 3); and
the second pMOS pass transistor coupled to the power supply line (“For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage.”, page 8, paragraph 3)
so that when the gate is at a positive voltage no current flows (page 8, paragraph 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov and Weste such that the first pMOS pass transistor coupled to the power supply line; and
the second pMOS pass transistor coupled to the power supply line
so that when the gate is at a positive voltage no current flows (id.).
In regards to claim 2, Liaw further teaches a word-line assist circuit coupled to the at least one word line (Controller 25, figure 1);
a first bit-line assist circuit and a second bit-line assist circuit respectively coupled to the first bit line and the second bit line (Controller 20, figure 1);
a power-supply assist circuit coupled to the power supply line (Controller 20, figure 1); and
a first ground-line assist circuit and a second ground-line assist circuit respectively coupled to the first ground line and the second ground line (Controller 20, figure 1).
In regards to claim 3, Liaw further teaches that the at least one word line includes two word lines (1st WL and 2nd WL, figure 5B) that are respectively coupled to the first pass transistor (Figures 6A-6C show how the gate of PG-1 is connected through gate via 260A, word line landing pad 280D, and via 285A to the 1st WL 290A) and the second pass transistor (Figures 6A-6E show how the gate of PG-2 is connected through gate via 260B, word line landing pad 280E, via 285B, 1st WL 290A, via 295C, word line landing pad 300C, and via 305 to the 2nd WL 310).
In regards to claim 4, Asenov further teaches that the first pass transistor and the second pass transistor are metal-oxide-semiconductor field effect transistors (abstract and figure 3).
In regards to claim 5, Liaw teaches a static random access memory device (“a static random-access memory (SRAM)”, paragraph 0004) comprising:
a plurality of word lines including at least one first word line (See WL’s, figure 1);
a plurality of bit lines including a first bit line, a second bit line, a third bit line, and a fourth bit line (See BL’s and BLB’s, figure 1);
a plurality of power supply lines including a first power supply line (VDD, figure 2) and a second power supply line (Figure 1 shows how the copies of SRAM cells are arranged);
a plurality of ground lines including a first ground line (1st VSS, figure 2), a second ground line (2nd Vss, figure 2), a third ground line, and a fourth ground line (Figure 1 shows how many copied of SRAM cells are arranged), wherein the plurality of power supply lines run in a direction parallel to the plurality of bit lines and the plurality of ground lines but perpendicular to the plurality of word lines (See figures 6B-6D which show the bit lines and ground lines running in the Y direction and the word lines running in the X direction); and
a plurality of static random access memory cells including a first static random access memory cell and a second static random access memory cell (See SRAM cells, figure 1);
wherein the first static random access memory cell including:
a first inverter and a second inverter cross-coupled and coupled to the first power supply line, wherein the first inverter is coupled to the first ground line, and the second inverter is coupled to the second ground line (Figure 2 shows cross-coupled inverters formed by PU-1 and PD-1 and PU-2 and PD-2, PU-1 and PU-2 are both coupled to VDD, PD-1 is coupled to 1st Vss, and PD-2 is connected to 2nd Vss);
a first pass transistor coupled to the at least one first word line, the first bit line, and the first inverter (See PG-1 in figure 2); and
a second pass transistor coupled to the at least one first word line, the second bit line, and the second inverter (See PG-2 in figure 2); and
wherein the second static random access memory cell including:
a third inverter and a fourth inverter cross-coupled and coupled to the second power supply line, wherein the third inverter is coupled to the third ground line, and the fourth inverter is coupled to the fourth ground line (Figure 2 shows cross-coupled inverters formed by PU-1 and PD-1 and PU-2 and PD-2, PU-1 and PU-2 are both coupled to VDD, PD-1 is coupled to 1st Vss, and PD-2 is connected to 2nd Vss; See also figure 1);
a third pass transistor coupled to the at least one first word line, the third bit line, and the third inverter (See PG-1 in figure 2; See also figure 1); and
a fourth pass transistor coupled to the at least one first word line, the fourth bit line, and the fourth inverter (See PG-2 in figure 2; See also figure 1).
Liaw fails to teach the first pass transistor coupled to the first power supply line,
the second pass transistor coupled to the first power supply line,
the third pass transistor coupled to the second power supply line, and
the fourth pass transistor coupled to the second power supply line.
Asenov teaches using a pMOS pass transistors (abstract and figure 3) which “can achieve: 1) improvements in writability; 2) improvements in readability while maintaining stability; and 3) flip the polarity of the bit line pre-charge from ‘1’ to ‘0’, which can prove beneficial when the pMOS pass gate is stronger than the nMOS pass gate” (Col. 3, lines 29-34). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov such that the first pass transistor, the second pass transistor, the third pass transistor, and the fourth pass transistor are all pMOS pass transistors which “can achieve: 1) improvements in writability; 2) improvements in readability while maintaining stability; and 3) flip the polarity of the bit line pre-charge from ‘1’ to ‘0’, which can prove beneficial when the pMOS pass gate is stronger than the nMOS pass gate” (id.).
Liaw in view of Asenov fails to teach the first pMOS pass transistor coupled to the first power supply line,
the second pMOS pass transistor coupled to the first power supply line,
the third pMOS pass transistor coupled to the second power supply line, and
the fourth pMOS pass transistor coupled to the second power supply line.
Weste teaches that pMOS pass transistors are coupled to a power supply line (“For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage.”, page 8, paragraph 3) so that when the gate is at a positive voltage no current flows (page 8, paragraph 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov and Weste such that the first pMOS pass transistor coupled to the first power supply line,
the second pMOS pass transistor coupled to the first power supply line,
the third pMOS pass transistor coupled to the second power supply line, and
the fourth pMOS pass transistor coupled to the second power supply line
so that when the gate is at a positive voltage no current flows (id.).
In regards to claim 7, Liaw further teaches that the plurality of static random access memory cells further includes a third static random access memory cell (See SRAM cells, figure 1), the plurality of word lines further includes at least one second word line (See WL’s, figure 1), and the third static random access memory cell includes:
a fifth inverter and a sixth inverter cross-coupled and coupled to the first power supply line, wherein the fifth inverter is coupled to the first ground line, and the sixth inverter is coupled to the second ground line (Figure 2 shows cross-coupled inverters formed by PU-1 and PD-1 and PU-2 and PD-2, PU-1 and PU-2 are both coupled to VDD, PD-1 is coupled to 1st Vss, and PD-2 is connected to 2nd Vss);
a fifth pass transistor coupled to the at least one second word line, the first bit line, and the fifth inverter (See PG-1 in figure 2); and
a sixth pass transistor coupled to the at least one second word line, the second bit line, and the sixth inverter (See PG-2 in figure 2).
Asenov further teaches that the fifth and sixth pass transistors are pMOS pass transistors (abstract and figure 3).
Weste further teaches that the fifth and sixth pMOS pass transistors are coupled to the first power supply line (“For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage.”, page 8, paragraph 3).
In regards to claim 9, Liaw further teaches that the plurality of static random access memory cells further includes a fourth static random access memory cell (See SRAM cells, figure 1), and the fourth static random access memory cell includes:
a seventh inverter and an eighth inverter cross-coupled and coupled to the second power supply line, wherein the seventh inverter is coupled to the third ground line, and the eighth inverter is coupled to the fourth ground line (Figure 2 shows cross-coupled inverters formed by PU-1 and PD-1 and PU-2 and PD-2, PU-1 and PU-2 are both coupled to VDD, PD-1 is coupled to 1st Vss, and PD-2 is connected to 2nd Vss);
a seventh pass transistor coupled to the at least one second word line, the third bit line, and the seventh inverter (See PG-1 in figure 2); and
an eighth pass transistor coupled to the at least one second word line, the fourth bit line, and the eighth inverter (See PG-2 in figure 2).
Asenov further teaches that the seventh and eighth pass transistors are pMOS pass transistors (abstract and figure 3).
Weste further teaches that the seventh and eighth pass transistors are coupled to the first power supply line (“For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage.”, page 8, paragraph 3).
In regards to claim 10, Asenov further teaches that the first pass transistor, the second pass transistor, the third pass transistor, the fourth pass transistor, the fifth pass transistor, the sixth pass transistor, the seventh pass transistor, and the eighth pass transistor are metal-oxide-semiconductor field effect transistors (abstract and figure 3).
In regards to claim 12, Liaw further teaches that the at least one second word line includes two second word lines (1st WL and 2nd WL, figure 5B) that are respectively coupled to the fifth pass transistor (Figures 6A-6C show how the gate of PG-1 is connected through gate via 260A, word line landing pad 280D, and via 285A to the 1st WL 290A) and the sixth pass transistor (Figures 6A-6E show how the gate of PG-2 is connected through gate via 260B, word line landing pad 280E, via 285B, 1st WL 290A, via 295C, word line landing pad 300C, and via 305 to the 2nd WL 310) and respectively coupled to the seventh pass transistor (Figures 6A-6C show how the gate of PG-1 is connected through gate via 260A, word line landing pad 280D, and via 285A to the 1st WL 290A) and the eighth pass transistor (Figures 6A-6E show how the gate of PG-2 is connected through gate via 260B, word line landing pad 280E, via 285B, 1st WL 290A, via 295C, word line landing pad 300C, and via 305 to the 2nd WL 310).
In regards to claim 13, Liaw further teaches a first word-line assist circuit coupled to the at least one first word line (Controller 25, figure 1);
a first bit-line assist circuit and a second bit-line assist circuit respectively coupled to first bit line and the second bit line (Controller 20, figure 1);
a first power-supply assist circuit coupled to the first power supply line (Controller 20, figure 1);
a first ground-line assist circuit and a second ground-line assist circuit respectively coupled to the first ground line and the second ground line (Controller 20, figure 1);
a third bit-line assist circuit and a fourth bit-line assist circuit respectively coupled to the third bit line and the fourth bit line (Controller 20, figure 1);
a second power-supply assist circuit coupled to the second power supply line (Controller 20, figure 1); and
a third ground-line assist circuit and a fourth ground-line assist circuit respectively coupled to the third ground line and the fourth ground line (Controller 20, figure 1).
In regards to claim 14, Liaw further teaches a second word-line assist circuit coupled to the at least one second word line (Controller 25, figure 1).
In regards to claim 15, Liaw further teaches that the at least one first word line includes two first word lines (1st WL and 2nd WL, figure 5B) that are respectively coupled to the first pass transistor (Figures 6A-6C show how the gate of PG-1 is connected through gate via 260A, word line landing pad 280D, and via 285A to the 1st WL 290A) and the second pass transistor (Figures 6A-6E show how the gate of PG-2 is connected through gate via 260B, word line landing pad 280E, via 285B, 1st WL 290A, via 295C, word line landing pad 300C, and via 305 to the 2nd WL 310) and respectively coupled to the third pass transistor (Figures 6A-6C show how the gate of PG-1 is connected through gate via 260A, word line landing pad 280D, and via 285A to the 1st WL 290A) and the fourth pass transistor (Figures 6A-6E show how the gate of PG-2 is connected through gate via 260B, word line landing pad 280E, via 285B, 1st WL 290A, via 295C, word line landing pad 300C, and via 305 to the 2nd WL 310).
Claims 6, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2022/0262730) in view of Asenov et al. (US 11,894,049), Weste et al. (CMOS VLSI Design), and Liaw (US 2021/0057023), subsequently referred to as ‘023.
In regards to claim 6, Liaw in view of Asenov and Weste teaches claim 5. Liaw in view of Asenov and Weste fails to teach that the first static random access memory cell and the second static random access memory cell are arranged symmetric to each other. ‘023 teaches that the first static random access memory cell and the second static random access memory cell are arranged symmetric to each other (“Specifically, the SRAM cell 200X is a mirror image of the SRAM cell 200 across the X axis”, paragraph 0043) “to enable higher packing densities” (paragraph 0043). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov, Weste, and ‘023 such that the first static random access memory cell and the second static random access memory cell are arranged symmetric to each other “to enable higher packing densities” (id.).
In regards to claim 8, Liaw in view of Asenov and Weste teaches claim 7. Liaw in view of Asenov and Weste fails to teach that the first static random access memory cell and the third static random access memory cell are arranged symmetric to each other. ‘023 teaches that the first static random access memory cell and the third static random access memory cell are arranged symmetric to each other (“the SRAM cell 200Y is a mirror image of the SRAM cell 200 across the Y axis”, paragraph 0043) “to enable higher packing densities” (paragraph 0043). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov, Weste, and ‘023 such that the first static random access memory cell and the third static random access memory cell are arranged symmetric to each other “to enable higher packing densities” (id.).
In regards to claim 11, Liaw in view of Asenov and Weste teaches claim 9. Liaw in view of Asenov and Weste fails to teach that the fourth static random access memory cell and the third static random access memory cell are arranged symmetric to each other, and the fourth static random access memory cell and the second static random access memory cell are arranged symmetric to each other. ‘023 teaches that the fourth static random access memory cell and the third static random access memory cell are arranged symmetric to each other, and the fourth static random access memory cell and the second static random access memory cell are arranged symmetric to each other (“the SRAM cell 200XY is a mirror image of the SRAM cell 200X across the Y axis or the SRAM cell 200Y across the X axis”, paragraph 0043) “to enable higher packing densities” (paragraph 0043). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liaw with Asenov, Weste, and ‘023 such that that the fourth static random access memory cell and the third static random access memory cell are arranged symmetric to each other, and the fourth static random access memory cell and the second static random access memory cell are arranged symmetric to each other “to enable higher packing densities” (id.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Honda (US 4,631,705) teaches a memory cell with two ground lines. Liaw (US 2008/0123462) teaches an SRAM cell with two supply voltage lines. Deng (US 2013/0021864) teaches an SRAM cell with the body of the pass transistors grounded and two VSS. Liaw (US 2013/0272056) teaches an SRAM cell with two supply voltage lines. Wong (US 9,293,192) teaches an SRAM cell with split ground. Wang (US 11,404,112) teaches several assist circuits. Chou (US 2025/0056782) teaches an SRAM cell with two ground lines. Chanemougame (TW 202234402) teaches an SRAM cell with multiple VSS lines. Yang et al. ("Scaling of 32nm Low Power SRAM with High-K Metal Gate") teaches an SRAM cell with dual grounds. Chang et al. ("A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme") teaches an SRAM cell with split word lines and split ground lines. The other art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu et al. ("On the Data Dependency of the Read Speed of Low-Voltage SRAM with VSS-Assist Circuitry") teaches related work by one of the inventors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 10 September 2026
