DETAILED ACTION
The Examiner acknowledges the applicant's submission of the amendment dated 7/29/2026.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 10-14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 2016/0179685) in view of Park (US 10,853,236).
Regarding Claim 1, Byun teaches a memory system, comprising:
a memory device (memory device 150 of Fig. 12); and
a memory controller coupled to the memory device (controller 130 of Fig. 12), wherein the memory controller is configured to perform operations comprising:
in response to receiving a first read command that indicates to read first data associated with a first address (step 1305 of Fig. 13, Paragraph 0159);
receiving the first data from the memory device (if the data is not hot, NO at step 1325 of Fig. 13, data is retrieved from the memory device at steps 1345-1350 of Fig. 13, Paragraph 0164-0165); and
storing the first data in a buffer of the memory controller (buffer corresponding to memory controller memory 144 of Fig. 1, which has a read buffer, Paragraph 0051, and therefore data from read requests are obviously at least temporarily stored in the read buffer);
in response to receiving a second read command that indicates to read the first data associated with the first address, wherein the second read command is received within a pre-set duration after receiving the first data from the memory device (step 1325 of Fig. 13, a “request frequency” is checked for the read command, step 0164, frequency indicating a number of reads within a pre-set duration, which may be “YES” if the data is accessed frequently enough, and is sent to the memory controller at step 1335 of Fig. 13);
receiving the first data from the memory device; and
storing the first data in the buffer of the memory controller (if another command is received for the same address at step 1305 of Fig. 13, and the data is now hot data, the data will be stored in buffer/cache 1240 of Fig. 12, “When the corresponding hot data [for a given read request from the host] are not the data stored in the segments 1242, 1244, 1246 and 1248 of the cache 1240, the controller 130 reads the corresponding hot data from the memory blocks 1250, 1260 and 1270 of the memory device 150, and processes the corresponding hot data, that is, performs a read/write operation, in the segments 1242, 1244, 1246 and 1248 of the cache 1240,” Paragraph 0157, also note “The cache 1240 may be included in the memory 144 of the controller 130,” Paragraph 0138), wherein the first data remains in the buffer after the second read command is completed (hot data will remain in the cache/buffer 1240 of Fig. 12, Paragraph 0154); and
in response to receiving a third read command that indicates to read the first data associated with the first address, wherein the third read command is received within the pre-set duration after receiving the second read command (step 1325 of Fig. 13, a “request frequency” is checked for the read command, step 0164, frequency indicating a number of reads within a pre-set duration, which may be “YES” if the data is accessed frequently enough, and is sent to the memory controller at step 1335 of Fig. 13);
sending the first data from the buffer without receiving the first data from the memory device (when a third read command is received at step 1305 of Fig. 13, Paragraph 0159, and the data is hot data already stored in buffer/cache 1240, data will be sent from the buffer at step 1340 of Fig. 13, Paragraph 0167).
However, the cited prior art does not explicitly teach a read command associated with a logical address.
Park teaches a read command containing a logical address (C11 L49-55).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the logical addresses of Park in the read commands of Byun so the host does not need to know the physical address of where data is stored in memory.
Regarding Claim 3, the cited prior art teaches the memory system of claim 1, wherein the operations comprise
in response to receiving the third read command that indicates to read the first data associated with the first logical address, determining whether the first data is stored in the buffer (“it is checked through the data read command or the data write command received from the host device 1200 that the corresponding hot data are the data stored in the segments 1242, 1244, 1246 and 1248 of the cache 1240, the controller 130 processes the corresponding hot data in the segments 1242, 1244, 1246 and 1248 of the cache 1240, as described above. When the corresponding hot data are not the data stored in the segments 1242, 1244, 1246 and 1248 of the cache 1240, the controller 130 reads the corresponding hot data from the memory blocks 1250, 1260 and 1270 of the memory device 150, and processes the corresponding hot data, that is, performs a read/write operation, in the segments 1242, 1244, 1246 and 1248 of the cache 1240,” Paragraph 0157); and
in response to determining that the first data is stored in the buffer, sending the first data from the buffer (data is sent from the buffer/cache, Paragraph 0167, step 1340 of Fig. 13).
Regarding Claim 4, the cited prior art teaches the memory system of claim 1, wherein a duration of executing the third read command is shorter than a duration of executing the first read command or the second read command (as the third command has data already in the cache/buffer, the duration is obviously shorter than accessing the memory, which occurs during the first and second commands).
Regarding Claim 5, the cited prior art teaches the memory system of claim 1, wherein the second read command is received from a host after the first read command is completed, and wherein the third read command is received from the host after the second read command is completed (the first read command corresponding to a request when the data is cold, the second read command corresponding to when data is first moved to the cache when the data becomes hot, and the third read command corresponding to when the request for data is already in the cache, and the commands may be received in succession).
Regarding Claim 10, the cited prior art teaches the memory system of claim 1, but Byun does not explicitly teach wherein a size of the first data is 4kB.
Park teaches wherein a size of first data is 4kB (“a read request of the host for the 4 KB data,” C11 L56-61).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the 4kB size of Park in the cited prior art in order to provide a uniform size of reading data from an address.
Regarding Claim 11, the cited prior art taches the memory system of claim 1, wherein the operations comprise:
in response to receiving the first read command, sending first read sequences to the memory device, wherein the first read sequences indicate to read the first data (the first read command corresponding to when data is cold, indicating a “NO” decision at step 1325, and a read sequence is sent to the memory device at step 1350 of Fig. 13, Paragraph 0163-0165); and
in response to receiving the second read command, sending second read sequences to the memory device, wherein the second read sequences indicate to read the first data (if another command is received for the same address at step 1305 of Fig. 13, and the data is now hot data, the data will be stored in buffer/cache 1240 of Fig. 12, “When the corresponding hot data [for a given read request from the host] are not the data stored in the segments 1242, 1244, 1246 and 1248 of the cache 1240, the controller 130 reads the corresponding hot data [via a read sequence] from the memory blocks 1250, 1260 and 1270 of the memory device 150, and processes the corresponding hot data, that is, performs a read/write operation, in the segments 1242, 1244, 1246 and 1248 of the cache 1240,” Paragraph 0157), and
wherein the memory controller does not send read sequences to the memory device in response to receiving the third read command (if the third request is received and the data is hot and stored in the cache, no sequence to the memory device is necessary, as the data is read from the cache/buffer at step 1340 of Fig. 13).
Regarding Claim 12, the cited prior art teaches the memory system of claim 1, wherein the operations comprise:
in response to receiving the first read command, receiving the first data from the memory device (the first read command corresponding to when data is cold, indicating a “NO” decision at step 1325, and a read sequence is sent to the memory device at step 1350 of Fig. 13, Paragraph 0163-0165); and
in response to receiving the second read command, receiving the first data from the memory device (if another command is received for the same address at step 1305 of Fig. 13, and the data is now hot data, the data will be stored in buffer/cache 1240 of Fig. 12, “When the corresponding hot data [for a given read request from the host] are not the data stored in the segments 1242, 1244, 1246 and 1248 of the cache 1240, the controller 130 reads the corresponding hot data [via a read sequence] from the memory blocks 1250, 1260 and 1270 of the memory device 150, and processes the corresponding hot data, that is, performs a read/write operation, in the segments 1242, 1244, 1246 and 1248 of the cache 1240,” Paragraph 0157), and
wherein the memory controller does not receive data from the memory device in response to receiving the third read command (if the third request is received and the data is hot and stored in the cache, no sequence to the memory device is necessary, as the data is read from the cache/buffer at step 1340 of Fig. 13).
Claim 13 is the memory controller corresponding to the memory system of claim 1, and is rejected under similar rationale.
Claim 14 is the memory controller corresponding to the memory system of claim 4, and is rejected under similar rationale.
Claim 19 is the memory controller corresponding to the memory system of claim 11, and is rejected under similar rationale.
Claim 20 is the method corresponding to the memory system of claim 11, and is rejected under similar rationale.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 2016/0179685) in view of Park (US 10,853,236) and Gold et al (US 2024/0354256).
Regarding Claim 2, the cited prior art teaches the memory system of claim 1, but does not explicitly teach wherein the operations comprise:
in response to receiving the first read command that indicates to read the first data associated with the first logical address:
storing the first data in the buffer of the memory controller; and
deleting the first data from the buffer after the first read command is completed.
Gold teaches in response to receiving a first read command that indicates to read the first data associated with the first logical address:
storing the first data in the buffer of the memory controller; and
deleting the first data from the buffer after the first read command is completed (Paragraph 0010).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the storing and deleting of Gold in the cited prior art in order to quickly provide read data to a host while ensuring enough room is in a buffer for hot data.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 2016/0179685) in view of Park (US 10,853,236) and Minopoli et al (US 2026/0029947).
Regarding Claim 7, the cited prior art teaches the memory system of claim 1, but does not explicitly teach wherein the operations further comprise:
after receiving the first read command, storing the first logical address in the memory controller.
Minopoli teaches after receiving a first read command, storing the first logical address in the memory controller (steps 310 and 335 of Fig. 3).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the storing of Minopli in the cited prior art in order to track hot data.
Claim 16 is the memory controller corresponding to the memory system of claim 7, and is rejected under similar rationale.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 2016/0179685) in view of Park (US 10,853,236), Minopoli et al (US 2026/0029947) and Gupta et al (US 2021/0263862).
Regarding Claim 8, the cited prior art teaches the memory system of claim 7, but does not explicitly teach wherein the operations comprise:
in response to receiving a fourth read command that indicates to read second data associated with a second logical address:
deleting the first data from the buffer; and
storing the second logical address in the memory controller in replacement of the first logical address.
Gupta teaches in response to receiving a fourth read command that indicates to read second data associated with a second logical address (corresponding to a read that hits in a lower perf. portion at step 602 of Fig. 6):
deleting first data from a buffer (data is removed from a buffer at step 608 of Fig. 6, Paragraph 0069); and
storing the second logical address in the memory controller in replacement of the first logical address (step 610 of Fig. 6, Paragraph 0069).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the deleting and storing of Gupta in the cited prior art in order to make room for data more likely to be used in the future.
Claim 17 is the memory controller corresponding to the memory system of claim 8, and is rejected under similar rationale.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 2016/0179685) in view of Park (US 10,853,236), Minopoli et al (US 2026/0029947) and Talagal et al (US 10,102,117).
Regarding Claim 9, the cited prior art teaches the memory system of claim 7, but does not explicitly teach wherein the operations comprise:
in response to receiving a write command or a trim command:
deleting the first data from the buffer; and
deleting the first logical address stored in the memory controller.
Talagala et al teaches:
in response to receiving a write command or a trim command (TRIM directive, C58 L1-17):
deleting the first data from the buffer (“The storage module 430 may be further configured to erase data associated with the logical identifiers,” C58 L1-17); and
deleting the first logical address stored in the memory controller (“the storage module 430 may be configured to invalidate data of the logical identifiers, which may comprise removing associations between the logical identifiers and the corresponding physical storage locations by, inter alia, removing and/or invalidating one or more entries,” C58 L1-17).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the trim command of Talagala in the cited prior art in order to remove data from a cache when it is no longer needed.
Claim 18 is the memory controller corresponding to the memory system of claim 9, and is rejected under similar rationale.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant’s arguments that the cited prior art fails to teach the claims as amended has been considered. Upon further search and consideration, the examiner believes the independent claims are obvious in view of Byun and Park as noted in the rejection above.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Benedict et al (US 2026/0030162) teaches CACHING DATA OF MEMORY ROWS.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-5, 7-14, and 16-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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