DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The preliminary amendment of May 2, 2025 has been entered.
Claims 21-40 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 10, 2025 and June 24, 2025 has been considered by the examiner. An initialed copy of each IDS is included with this Office Action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or canceled from the claims:
a sample circuit in claim 21, lines 8-15;
the control circuitry in claim 24; and
a second component configured to activate two ADC circuits based on the first and second baud rates, respectively, in claim 38.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
The claims are objected to because of the following informalities:
in claim 21, line 1, the comma after “apparatus” should be deleted;
in claim 22, line 5, “sub-ADCs circuits” should be “sub-ADC circuits”;
in claim 22, line 7, “sub-ADCs” should be “sub-ADC circuits”;
in claim 31, line 1, the comma after “method” should be deleted;
in claim 32, line 5, “sub-ADCs circuits” should be “sub-ADC circuits”;
in claim 32, line 7, “sub-ADCs” should be “sub-ADC circuits”;
in claim 38, line 1, the comma after “system” should be deleted;
in claim 39, line 5, “sub-ADCs circuits” should be “sub-ADC circuits”;
in claim 39, line 7, “sub-ADCs” should be “sub-ADC circuits”; and
dependent claim(s) are objected to under the same ground(s) as the claim(s) from which it depends.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24 and 34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification of the parent and present applications, at the time the application was filed, does not describe “a control circuitry configured to provide a clock circuit to the first ADC circuit and configured to gate a clock signal to the second ADC circuit” as recited in the respective claims. The specification of the parent and present applications, at the time the application was filed, describes selecting the first or second ADC circuits (see paragraphs [0036]-[0037] and [0070]-[0071] of the present application) but does not describe the “control circuitry” as recited in the respective claims. Therefore, claims 24 and 34 fail to comply with the written description requirement.
Claims 23, 24, 34 and 38-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claim 23, it does not make sense that “the first ADC circuit has greater power consumption than the first ADC circuit” (see line 3) (i.e. an ADC circuit has greater power consumption than itself). It appears that the second occurrence of “first ADC circuit” should be “second ADC circuit.”
With regard to claim 24, it is unclear what is meant by “the control circuit is configured to provide a clock circuit to the first ADC circuit” on lines 1-2. It is unclear how a “clock circuit” is provided to the first ADC circuit.
Similarly, with regard to claim 34, it is unclear what is meant by “providing a clock circuit to the first ADC circuit” on lines 1-2. It is unclear how a “clock circuit” is provided to the first ADC circuit.
With regard to claim 38, it is unclear whether the “first analog-to-digital (ADC) circuit” and the “second ADC circuit” on lines 12 and 16, respectively, are part of the “system” or the “second component.”
Dependent claim(s) are rejected under the same ground(s) as the claim(s) from which it depends.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21, 23, 25, 31, 33, 35 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US Patent No. 8,369,458 B2) in view of Azenkot et al. (US Patent No. 10,404,496 B1) and Kou (US Patent No. 9,461,654 B1).
With regard to claims 21 and 31, FIG. 2 of Wong et al. discloses the claimed invention including an apparatus comprising a “front end circuit” (RFIC 102) and a “sample circuit” (ADC system 105) that includes a first analog-to-digital converter circuit having a first resolution (see column 2, lines 38-55 and column 2, line 67 – column line 4); a second analog-to-digital converter circuit having a second resolution (see column 2, lines 38-55 and column 2, line 67 – column line 4); and control circuitry configured to select the first and second ADC circuit based on the first and second data rates, respectively (see column 2, lines 38-55 and column 3, lines 10-11 wherein it is implicit that there is circuitry for “selecting” the appropriate ADC for the different data rates) wherein the apparatus performs the corresponding steps recited in the method of claim 31. However, Wong et al. does not disclose selecting the respective ADC circuits based on the baud rate nor does Wong et al. disclose that the front-end circuit is configured to: generate a first equalized signal based on a first input signal that encodes a first serial data stream that has a plurality of data symbols and has a first baud rate and generate a second equalized signal based on a second input signal that encodes a second serial data stream that has a plurality of data symbols and has a second baud rate.
Since Azenkot et al. teaches that “data rate” may correspond to any suitable data rate unit (e.g. baud rate) (see column 4, lines 53-55), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use any known corresponding data rate unit (e.g. baud rate) to select the ADC circuit in Wong et al. to obtain predictable results since the specific data rate unit for selecting the ADC circuit does not affect the functionality of the ADC circuit itself.
FIG. 2 of Kou discloses a high speed communication system with a receiver that includes front end circuit (AFE 210) that provides an equalized signal to a plurality of ADC circuits. (See column 4, lines 3-11) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “front-end circuit” of Wong et al. in view of Azenkot et al. to generate an equalized signal in order to compensate for channel impairments to improve data recovery. Since the “front-end circuit” in the receiver of Wong et al. in view of Azenkot et al. and Kou processes/equalizes any input signal and the receiver of Wong et al. in view of Azenkot et al. receives signals having different data rate (see “high, medium, and low” data rates in Wong et al., column 2, lines 38-30), it is inherent that the front-end circuit of the receiver disclosed by Wong et al. in view of Azenkot et al. and Kou will generate a corresponding equalized signal for a signal having the either first and second baud rate thereby reading on the claim limitation in claim 21, lines 2-7 and claim 31, lines 2-6, respectively.
With regard to claim 23, Wong et al. in view of Azenkot et al. and Kou disclose the claim invention including the first resolution being greater than the second resolution. (See Wong et al., column 2, lines 42-51) Interpreting the second occurrence of “the first ADC circuit” on line 3 as “the second ADC circuit” (see the rejection of claim 23 under 35 U.S.C. 112(b) above), Wong et al. in view of Azenkot et al. and Kou also disclose the first ADC circuit as having greater power consumption than the second ADC circuit (see column 2, lines 52-54 which discloses that a lower resolution ADC has lower power consumption).
With regard to claims 25 and 35, Wong et al. in view of Azenkot et al. and Kou disclose the claim invention including the “second” ADC circuit having a longer resolution period duration than the “first” ADC circuit. Since each of the ADC circuits in Wong et al. in view of Azenkot et al. and Kou have a different resolution, it is implicit that each ADC with a different resolution period duration wherein one of the resolution period durations will be longer than another one of the resolution period durations.
With regard to claim 33, Wong et al. in view of Azenkot et al. and Kou disclose sampling by first ADC circuit utilizes more power than sampling by the second ADC circuit (see column 2, lines 52-54 which discloses that a lower resolution ADC has lower power consumption).
With regard to claim 38, FIG. 2 of Wong et al. discloses the claimed invention including a system comprising a “second component” (100) configured to receive signals; activate, based on a first data rate, a first ADC circuit; and activate, based on a second data rate, a second ADC circuit (see column 2, lines 38-55 and column 3, lines 10-11 wherein it is implicit that there is circuitry for “selecting” the appropriate ADC for the different data rates). Although Wong does not explicitly disclose a “first component” configured to generate data streams having respective data/baud rates and transmit signals that encode the data streams, it is implicit that a transmitter (i.e. “a first component”) generates and transmits signals to the receiver of Wong et al. thereby reading on the “first component” in claim 38, lines 2-7. However, Wong et al. does not disclose selecting the respective ADC circuits based on the baud rate nor does Wong et al. disclose generate a first equalized signal based on a first input signal and generating a second equalized signal based on a second input signal.
Since Azenkot et al. teaches that “data rate” may correspond to any suitable data rate unit (e.g. baud rate) (see column 4, lines 53-55), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use any known corresponding data rate unit (e.g. baud rate) to select the ADC circuit in Wong et al. to obtain predictable results since the specific data rate unit for selecting the ADC circuit does not affect the functionality of the ADC circuit itself.
FIG. 2 of Kou discloses a high speed communication system with a receiver that includes front end circuit (AFE 210) that provides an equalized signal to a plurality of ADC circuits. (See column 4, lines 3-11) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “second component” of Wong et al. in view of Azenkot et al. to generate an equalized signal in order to compensate for channel impairments to improve data recovery. Since the “second component” in Wong et al. in view of Azenkot et al. and Kou processes/equalizes any input signal and the receiver of Wong et al. in view of Azenkot et al. and Kou receives signals having different data rate (see “high, medium, and low” data rates in Wong et al., column 2, lines 38-30), it is inherent that the “second component” of the receiver disclosed by Wong et al. in view of Azenkot et al. and Kou will generate a corresponding equalized signal for a signal having either the first and second baud rate thereby reading on the claim limitation in claim 38, lines 11 and 15.
Claims 22, 32 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. in view of Azenkot et al. and Kou as applied to claims 21, 31 and 38, respectively, above, and further in view of Ramakrishnan et al. (US Patent No. 11,569,827 B1). Wong et al. in view of Azenkot et al. and Kou disclose the claimed invention except for the first ADC circuit including a first sub-ADC circuit; a second sub-ADC circuit; and control circuitry configured to sequentially operate the first and second sub-ADC circuits and interleave the outputs. FIG. 1 of Ramakrishnan et al. discloses an ADC circuit that includes a first sub-ADC circuit (e.g. 104-0); a second sub-ADC circuit (e.g. 104-1); and control circuitry (112 and 110) configured to sequentially operate the first and second sub-ADC circuits and interleave the outputs. (See abstract; column 1, lines 22-26 and 47-48; and column 3, lines 23-48) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention use the ADC of Ramakrishnan et al. as the first ADC circuit in Wong et al. in view of Azenkot et al. and Kou in order to achieve a high speed ADC using slower, power-efficient sub-converter units.
Claims 28, 29 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. in view of Azenkot et al. and Kou as applied to claims 21 and 31, respectively, above, and further in view of Liu et al. (US Patent No. 9,667,407 B1).
With regard to claim 28, Wong et al. in view of Azenkot et al. and Kou disclose the claimed invention except for clock circuitry configured to provide a clock signal to the selected ADC circuit. Liu et al. discloses “clock circuitry” configured to provide a clock signal to an ADC circuit. (See FIGs. 3 and 4; column 4, lines 6-11; and column 5, lines 1-7) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the clock recovery module of Liu et al. with the circuit of Wong et al. in view of Azenkot et al. and Kou in order to correct sampling timing to facilitate data recovery/demodulation.
With regard to claim 29, Wong et al. in view of Azenkot et al., Kou and Liu et al. disclose the claimed invention including the clock circuitry being configured to generate the clock signal based on the phase error information generated by the ADC circuit. (See Liu et al., 318 in FIGs. 3 and 4)
With regard to claim 37, Wong et al. in view of Azenkot et al. and Kou disclose the claimed invention except for generating a first clock for the first ADC circuit based on first error information from the first ADC circuit and generating a second clock for the second ADC circuit based on second error information from the second ADC circuit. Liu et el. discloses a clock recovery circuit that generates a clock for each ADC based on error information from the respective ADC circuit. (See FIGs. 3 and 4; column 4, lines 6-11; and column 5, lines 1-7) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the clock recovery module of Liu et al. with the circuit of Wong et al. in view of Azenkot et al. and Kou in order to correct sampling timing to facilitate data recovery/demodulation.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. in view of Azenkot et al. and Kou as applied to claim 21 above, and further in view of Palusa et al. (US Patent No. 10,904,044 B2). Wong et al. in view of Azenkot et al. and Kou disclose the claimed invention except for the front-end circuit including a filter circuit and a gain control circuit. FIG. 2 of Palusa et al. discloses a front-end circuit that includes a filter circuit and a gain control circuit. (See column 4, lines 21-39) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include both a filter circuit and a gain control circuit in the receiver disclosed by Wong et al. in view of Azenkot et al. and Kou in order to further compensate for channel impairments to improve data recovery.
Allowable Subject Matter
Claims 26, 27 and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Please note that non-cited portions of the respective references may also read on the claim limitations. Therefore, the references should be considered in their entirety.
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/BETSY DEPPE/Primary Examiner, Art Unit 2633
Prosecution Insights