DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 05/13/2024. It is noted, however, that applicant has not filed a certified copy of the JP2024-077644 application as required by 37 CFR 1.55.
Examiner’s Remarks
Fig 9: “deployable” and “undeployable” should have “status” added after for clarity in steps S308 and S309
Drawings
Figures 1-10 are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(1), which requires that every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner finds that the lines in drawings are pixelated, likely because the applicant did not use black (RGB=000). This means the final drawings may not print properly or may print with reduced quality. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Apparatus and Method for Scheduling CPUs, CPU Cores, and Accelerators for Related Tasks.
The disclosure is objected to because of the following informalities:
Par. [013], line 8: “bus” should be added after “inter-CPU”
Par. [017], line 4: “include” should be corrected to “includes”
Par. [017], line 5: “both of the number of” should be corrected to “both the number of”
Par. [019], line 3: “a plurality of accelerator 30” needs to be pluralized
Par. [021], line 2: “six accelerator 30” should be pluralized
Par. [023], line 1: “Application activation processing 41 is processing of” should be corrected to “application activation processing 41 is the process of’
Par. [025], line 3: “are” should be corrected to “is”
Par. [037]: “core allocation processing is processing of selecting” should be “core allocation processing is the process of selecting”
Par. [050], line 5: “the processing is processing performed to” should be corrected to “the processing is performed to”
Par. [062], line 1: “request processing is processing in which” should be corrected to “request processing is a process in which”
Par. [070], line 1: the “as processing” before “in S302” should be removed
Appropriate correction is required.
Claim Objections
Claims 3, 4, and 5 are objected to because of the following informalities:
“selects the accelerator” in claims 2-5 should be corrected to “selects an accelerator” to avoid antecedent basis issues
Appropriate correction is required.
Claim InterpretationThe following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is: “controller configured to…” in claims 1-5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner’s Remark: The examiner suggests altering the language to recite “control circuitry” in order to avoid U.S.C. 112 (a) and (b) issues.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to implement the selecting of the two or more CPU cores. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 2-5 are rejected for inheriting the deficiencies of claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, claim limitation “a controller configured to perform control of selecting two or more CPU cores of the plurality of CPU cores” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The application does not disclose adequate structure to perform the claimed function. The specification discloses a control unit/CPU, but there is no disclosure of any corresponding algorithm configured to perform the listed functionality. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 2-5 are rejected for inheriting the deficiencies of claim 1.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 and 6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites an apparatus for processing information.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites “selecting two or more CPU cores of the plurality of CPU cores…, from one physical CPU of the plurality of physical CPUs”. This limitation covers a mental process(Par. [037], “The CPU core allocation processing is the processing of selecting one CPU core from among a plurality of CPU cores”; although implemented on a computer, this limitation amounts to mere selecting between a plurality of components, which can be done by the human mind. See MPEP 2106(a)(III)(C)), and therefore the limitation falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites “a plurality of physical CPUs each including a plurality of CPU cores”, “a controller”, and that the cores “are caused to execute an application to be executed using the two or more CPU cores, from one physical CPU of the plurality of physical CPUs”. The additional elements are recited at a high level of generality, i.e. as generic computer components performing a computer function of executing instructions and processing data. These elements fail to provide a meaningful limitation on the judicial exception and amount to no more than mere instructions to apply the exception using generic computer components. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements to amount to significantly more than the judicial exception. As previously discussed, the claimed elements amount to no more than instructions to apply the exception even when taken as a whole. Therefore, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim beyond the judicial exception, and fails to ensure the claim amounts to significantly more than the judicial exception itself. Therefore, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 further recites “wherein the controller selects the two or more CPU cores in ascending order of usage rates from among the plurality of CPU cores included in the one physical CPU”. This limitation covers a mental process in the same manner as claim 1. The claim does not recite any additional elements that would integrate the judicial exception under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent eligible under 35 U.S.C. 101. Claim 3 further recites “wherein the controller selects the accelerator to be used in execution of the application, from among the accelerators included under the one physical CPU”. This limitation amounts to a mental process in the same manner as claim 1.
Under step 2A, the claim recites the additional limitation “wherein each of the plurality of physical CPUs includes a plurality of accelerators thereunder”. The additional elements are recited at a high level of generality, i.e. as generic computer components performing a computer function of executing instructions and processing data. These elements fail to provide a meaningful limitation on the judicial exception and amount to no more than mere instructions to apply the exception using generic computer components. Thus, the claim is directed to an abstract idea.
Under step 2B, the claim does not include additional elements to amount to significantly more than the judicial exception. As previously discussed, the claimed elements amount to no more than instructions to apply the exception even when taken as a whole. Therefore, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim beyond the judicial exception, and fails to ensure the claim amounts to significantly more than the judicial exception itself. Therefore, the claim is not patent-eligible under 35 U.S.C 101.
Claim 6 is the method claim corresponding to claim 1, and is rejected on the same grounds
Claim Rejections - 35 USC § 103The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US20130312002A1 Hiromasa et Al in view of US20100169892A1 Stam et al, referred to as Hiromasa and Stam hereout.
Regarding Claim 1, Hiromasa teaches an information processing apparatus (Par. [019], “scheduling method and scheduling system”) comprising:
a plurality of physical CPUs (Fig 1, “CPU #0” and “CPU #1”; Par. [019], “In the embodiment, for simplification of the description, description will be made taking an example of a group of single-core processors connected in parallel) and
a controller configured to perform control of selecting a CPU of the plurality of CPUs that is caused to execute an application to be executed ... using ... one physical CPU of the plurality of physical CPUs (Par. [037] “The scheduler 101 selects a CPU to execute the app #5”)
However, Hiromasa does not teach that each of the CPUs include a plurality of CPU cores. Hiromasa also does not teach selecting two or more CPU cores of the plurality of CPU cores from one physical CPU that are caused to execute an application.
Stam teaches a CPU comprising a plurality of CPU cores (Fig. 2, “core 1” through “core 4”).
It would be obvious to one of ordinary skill in the art, with the teachings of Hiromasa and Stam before them, to modify Hiromasa to implement each CPU including a plurality of cores, as taught by Stam. This would amount to a simple substitution of one known element for another to obtain predictable results (See MPEP 2144(I)(B)).
The combination still does not teach selecting two or more CPU cores of the plurality of CPU cores from one physical CPU that are caused to execute an application.
Stam further teaches executing an application on a plurality of cores of a CPU (Par.[008], “ Embodiments disclosed herein include an accelerator module that modifies a single application to run on multiple processing cores of a single CPU”; Fig 2, “App A: WL1” through “App A: WL4”; this shows the application “A” being split into several workloads to run parallel on several cores).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, with the teachings of Hiromasa and Stam before them, to implement execution of an application on the plurality of cores of a CPU of Hiromasa. As Hiromasa teaches selecting a CPU, the combination would result in selecting two or more cores of the plurality of CPU cores from one physical CPU to execute the application. One of ordinary skill in the art would be motivated to do so in order to execute more applications in parallel and thus increase the processing power of the system.
Claim 6 is a method claim corresponding to claim 1, and is rejected on the same grounds.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hiromasa and Stam, further in view of US20190042307A1 Sivakumar et al, referred to as Sivakumar.
Regarding Claim 2, Hiromasa and Stam teach the information processing apparatus according to claim 1 as shown above. However, Hiromasa and Stam do not teach wherein the controller selects the two or more CPU cores in ascending order of usage rates from among the plurality of CPU cores included in the one physical CPU.
Sivakumar teaches select(Ing) a single CPU core with the least usage rate from among the plurality of CPU cores included in the one physical CPU(Par. [018] “a core may be selected from the plurality of processor cores at block 26 in response to the selected core being available while satisfying the least used condition”; This source selects the least used core when selecting a core for a new task for the purpose of uniform temperature wear uniformly over time)
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, with the teachings of Hiromasa, Stam, and Sivakumar before them, to implement the least used condition of Sivakumar onto the invention of claim 1, in order to increase the reliability of the invention by distributing the wear on the cores evenly in the same manner as in Sivakumar(Par. [018], “Thus, every time a core is selected for a ready thread, the least used cores are given higher preference/priority over other available cores. This approach ensures that the cores not only operate within their safe thermal range, but wear uniformly and therefore exhibit greater reliability”). Doing so on a processor that selects multiple cores at a time to run multiple applications would necessarily involve picking the least used for one application, then the next least used for the next application, and so on until all applications are scheduled; or, put another way, picking the cores in ascending order of usage rates in the same way as the claimed invention of the instant application.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hiromasa in view of Stam, further in view of US20240095070A1 Kim et Al, referred to here as Kim.
Regarding Claim 3, Hiromasa and Stam teach the information processing apparatus according to claim 1 as shown above.
However, Hiromasa and Stam do not teach wherein each of the plurality of physical CPUs includes a plurality of accelerators thereunder
Hiromasa and Stam also do not teach wherein the controller selects the accelerator to be used in execution of the application, from among the accelerators included under the one physical CPU.
Kim teaches a physical CPU that selects an accelerator to be used in the execution of an application, from among a plurality of accelerators thereunder(Fig 2; Par. [054] “the system including a heterogeneous accelerator pool may include a host for managing a heterogenous accelerator pool”; The host is a CPU coupled to an accelerator pool; Par. [068] “the host processor selects the accelerator … to which the task is to be assigned”)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of claim 1 by coupling the accelerator pool from Kim with the CPUs of the Hiromasa and Stam, to allow for offloading and more efficient processing. This would involve using the controller from the combination of Hiromasa and Stam to select an accelerator, in the same method of selecting the CPU or CPU cores as above.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hiromasa in view of Stam and Kim, as applied to claim 3 above, and further in view of US20210389993A1 Cheng et Al, referred to herein as Cheng
Regarding Claim 4, Hiromasa, Stam, and Kim teach the information processing apparatus according to claim 3.
This combination does not teach wherein the controller selects the accelerator to be used in execution of the application, from among the accelerators in a standby state among the accelerators included under the one physical CPU.
Cheng teaches accelerator to be used in execution of the application … in a standby state (Par. [041], “DP accelerators not assigned to a group of DP accelerators can be set to a low-power state… A low-power state can include reducing a clock speed of the DP accelerator or entering a standby state wherein the DP accelerator is still communicatively coupled to the host device and can be brought to a run state wherein the DP accelerator is ready to receive processing tasks from the host device”)
It would be obvious, to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hiromasa, Stam, and Kim by further putting the unused accelerators into a standby state when not in use, such as in Cheng, thus saving power. These accelerators would then be selected from when scheduling a new application.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hiromasa in view of Stam, Kim and Cheng, further in view of US20200174838A1 Li et Al, referred to as Li herein.
Regarding Claim 5, the combination of Hiromasa, Stam, Kim and Cheng teaches the information processing apparatus according to claim 4 as shown above. The combination thus far does not teach wherein the controller acquires information regarding a number of the accelerators to be used in execution of the application, and in a case where the number is equal to or smaller than the number of the accelerators in the standby state that are included under the one physical CPU, selects the accelerator to be used in execution of the application, from among the accelerators in the standby state.
Li teaches acquiring information regarding the number of accelerators to be used in the execution of the application as well as selecting the accelerators to be used in the execution of the application(Par. [068], “The type(s) and number(s) of accelerators are sometimes referred to herein as “accelerator requirements”; “A basic goal of the system is to select the accelerators that match the accelerator requirements”),
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the teachings of Li described above into the combination of claim 4, for the purpose of streamlining the process of selecting accelerators for an application. This would also involve selecting the accelerators from among those in the standby state, under the same rationale as claim 4.
Conclusion
The prior art made of record and not relied upon is considered relevant to the applicant’s disclosure. Relevant art:
US 20220237040 A1 Shin et Al; Allocation of multiple tasks to multiple accelerators
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN T KYZAR whose telephone number is (571)270-1463. The examiner can normally be reached 7:30a.m. - 5:00p.m. M-F ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joyti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.T.K./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
Prosecution Insights