DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 12-13, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0267881 hereinafter Feng) in view of Qing et a. (US 12,106,722 hereinafter Qing).
Referring to claim 1, Feng discloses a gate driving circuit (Fig. 1; a gate drive circuit 100), comprising a plurality of cascaded shift registers ([0040]; In the above display panel provided in embodiments of the present disclosure, the gate drive circuit includes shift registers cascaded to each other), wherein a shift register (Fig. 2; shift register) of the plurality of cascaded shift registers comprises a first input unit (Fig. 2; T1), a second input unit (Fig. 2; T2), a first output unit (Fig. 2; T3), a second output unit (Fig. 2; T8), a first reset unit (Fig. 2; T5) and a turn-off unit (Fig. 2; T4);
an output terminal of the first input unit (Fig. 2; T1) and a control terminal of the first output unit (Fig. 2; T3) are connected to a first node (Fig. 2; N2), and an output terminal of the second input unit (Fig. 2; T2) and a control terminal of the second output unit (Fig. 2; T8) are connected to a third node (Fig. 2; N3);
the first reset unit (Fig. 2; T5) comprises a first reset transistor (Fig. 2; T5), a gate of the first reset transistor (Fig. T5) is connected to a first clock signal terminal (Fig. 2; T5’s gate is connected to clock CK) or a third clock signal terminal, and a first electrode of the first reset transistor (Fig. 2; T5) is connected to the first node (Fig. 2; T5’s gate is connected to first Node N2 via Node N3 and T7); and
a control terminal of the turn-off unit (Fig. 2; T4) is connected to the first node (Fig. 2; Node 2) (Fig. 2; T4’s gate is connected to Node N2), a first terminal of the turn-off unit (Fig. 2; T4) is connected to a second electrode of the first reset transistor (Fig. 2; T5) and is configured to write a turn-on voltage into the second electrode of the first reset transistor (Fig. 2; T5) in response to the first node (Fig. 2; Node N2) controlling the turn-off unit to turn on ([0045]; the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.), and the turn-on voltage is a voltage for controlling the first output unit (Fig. 2; T3) to turn on ([0045]; an seventh transistor T7 is conducted, and the first clock control signal with the low level is transmitted to the second node N2 by the seventh transistor T7. For example, Vth7 represents a threshold voltage of the seventh transistor T7; Vth1 represents the threshold voltage of the first transistor T1; if Vth1<Vth7+Vth2, a voltage of the second node N2 is VL−Vth7−Vth2; and if Vth1>Vth7+Vth2, the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.).
However, Feng does not explicitly disclose the first reset unit is configured to write a turn-off voltage into the first node, and the turn-off voltage is a voltage for controlling the first output unit to turn off.
In analogous art, Qing discloses the first reset unit is configured to write a turn-off voltage into the first node (Qing- Fig. 2; Node N2), and the turn-off voltage is a voltage for controlling the first output unit to turn off (Qing- Col. 13 lines 48-53, Fig. 2; The second transistor T2 transmits the first voltage signal to the second node N2, such that the voltage of the second node N2 is at a high level. The fourth transistor T4 is turned off under the control of the voltage of the second node N2, and the first voltage signal charges the third capacitor C3.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Qing to the system of Feng in order to provide a display with high contrast, low power consumption, extremely high reaction speed, light and thin, bendable and low cost.
Referring to claim 2, Feng discloses wherein the turn-off unit (Fig. 2; T4) comprises a turn-off transistor (Fig. 2; T4), a gate of the turn-off transistor is connected to the first node (Fig. 2; T4’s gate is connected to first Node N2), and a first electrode of the turn-off transistor (Fig. 2; T4) is connected to the second electrode of the first reset transistor (Fig. 2; T5) (Fig. 2; T4’s gate is connected to reset transistor T5).
Referring to claim 3, Feng discloses wherein a second electrode of the turn-off transistor (Fig. 2; T4) is connected to a first power supply voltage terminal (Fig. 2; Voltage VGH), and the first power supply voltage terminal provides the turn-on voltage (Fig. 2; Voltage VGH provides a turn-on voltage).
Referring to claim 4, Feng discloses wherein a second electrode of the turn-off transistor (Fig. 2; T4) is connected to the first clock signal terminal or a second clock signal terminal (Fig. 2; T4’s electrode is connected to first clock signal terminal via gate of T5).
Referring to claim 12, Feng discloses wherein the gate of the first reset transistor (Fig. 2; T5) is connected to the first clock signal terminal (Fig. 2; T5’s gate is connected to clock CK), and the second electrode of the first reset transistor (Fig. 2; T5) is connected to the output terminal of the first input unit (Fig. 2; T5’s gate is connected to output terminal T1 via Node N3 and T7).
Referring to claim 13, Feng discloses wherein the first input unit comprises a first
input transistor (Fig. 2; T1), a gate of the first input transistor is connected to the first clock signal terminal (Fig. 2; T1’s gate is connected to first clock signal end CB), a first electrode of the first input transistor (Fig. 2; T1) is connected to a cascade signal input terminal (Fig. 2; T1’s first electrode is connected to signal input terminal VGL), and a second electrode of the first input transistor is connected to the second electrode of the first reset transistor (Fig. 2; T5) (Fig. 2; T1’s second electrode is connected to the second electrode of reset transistor T5 via T7 and Node N3).
Referring to claim 18, Feng discloses a display panel (Fig. 1; display panel), comprising a gate driving circuit (Fig. 1; a gate drive circuit 100), wherein the gate driving circuit (Fig. 1; a gate drive circuit 100) comprises a plurality of cascaded shift registers ([0040]; In the above display panel provided in embodiments of the present disclosure, the gate drive circuit includes shift registers cascaded to each other), and a shift register (Fig. 2; shift register) of the plurality of cascaded shift registers comprises a first input unit (Fig. 2; T1), a second input unit (Fig. 2; T2), a first output unit (Fig. 2; T3), a second output unit (Fig. 2; T8), a first reset unit (Fig. 2; T5) and a turn-off unit (Fig. 2; T4);
an output terminal of the first input unit (Fig. 2; T1) and a control terminal of the first output unit (Fig. 2; T3) are connected to a first node (Fig. 2; N2), and an output terminal of the second input unit (Fig. 2; T2) and a control terminal of the second output unit (Fig. 2; T8) are connected to a third node (Fig. 2; N3);
the first reset unit (Fig. 2; T5) comprises a first reset transistor (Fig. 2; T5), a gate of the first reset transistor (Fig. T5) is connected to a first clock signal terminal (Fig. 2; T5’s gate is connected to clock CK) or a third clock signal terminal, and a first electrode of the first reset transistor (Fig. 2; T5) is connected to the first node (Fig. 2; T5’s gate is connected to first Node N2 via Node N3 and T7); and
a control terminal of the turn-off unit (Fig. 2; T4) is connected to the first node (Fig. 2; Node 2) (Fig. 2; T4’s gate is connected to Node N2), a first terminal of the turn-off unit (Fig. 2; T4) is connected to a second electrode of the first reset transistor (Fig. 2; T5) and is configured to write a turn-on voltage into the second electrode of the first reset transistor (Fig. 2; T5) in response to the first node (Fig. 2; Node N2) controlling the turn-off unit to turn on ([0045]; the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.), and the turn-on voltage is a voltage for controlling the first output unit (Fig. 2; T3) to turn on ([0045]; an seventh transistor T7 is conducted, and the first clock control signal with the low level is transmitted to the second node N2 by the seventh transistor T7. For example, Vth7 represents a threshold voltage of the seventh transistor T7; Vth1 represents the threshold voltage of the first transistor T1; if Vth1<Vth7+Vth2, a voltage of the second node N2 is VL−Vth7−Vth2; and if Vth1>Vth7+Vth2, the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.).
However, Feng does not explicitly disclose the first reset unit is configured to write a turn-off voltage into the first node, and the turn-off voltage is a voltage for controlling the first output unit to turn off.
In analogous art, Qing discloses the first reset unit is configured to write a turn-off voltage into the first node (Qing- Fig. 2; Node N2), and the turn-off voltage is a voltage for controlling the first output unit to turn off (Qing- Col. 13 lines 48-53, Fig. 2; The second transistor T2 transmits the first voltage signal to the second node N2, such that the voltage of the second node N2 is at a high level. The fourth transistor T4 is turned off under the control of the voltage of the second node N2, and the first voltage signal charges the third capacitor C3.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Qing to the system of Feng in order to provide a display with high contrast, low power consumption, extremely high reaction speed, light and thin, bendable and low cost.
Referring to claim 19, Feng discloses wherein the turn-off unit (Fig. 2; T4) comprises a turn-off transistor (Fig. 2; T4), a gate of the turn-off transistor is connected to the first node (Fig. 2; T4’s gate is connected to first Node N2), and a first electrode of the turn-off transistor (Fig. 2; T4) is connected to the second electrode of the first reset transistor (Fig. 2; T5) (Fig. 2; T4’s gate is connected to reset transistor T5).
Referring to claim 20, Feng discloses a display device, comprising a display panel (Fig. 1; display panel) wherein the display panel comprises a gate driving circuit (Fig. 1; a gate drive circuit 100), the gate driving circuit (Fig. 1; a gate drive circuit 100) comprises a plurality of cascaded shift registers ([0040]; In the above display panel provided in embodiments of the present disclosure, the gate drive circuit includes shift registers cascaded to each other), and a shift register (Fig. 2; shift register) of the plurality of cascaded shift registers comprises a first input unit (Fig. 2; T1), a second input unit (Fig. 2; T2), a first output unit (Fig. 2; T3), a second output unit (Fig. 2; T8), a first reset unit (Fig. 2; T5) and a turn-off unit (Fig. 2; T4);
an output terminal of the first input unit (Fig. 2; T1) and a control terminal of the first output unit (Fig. 2; T3) are connected to a first node (Fig. 2; N2), and an output terminal of the second input unit (Fig. 2; T2) and a control terminal of the second output unit (Fig. 2; T8) are connected to a third node (Fig. 2; N3);
the first reset unit (Fig. 2; T5) comprises a first reset transistor (Fig. 2; T5), a gate of the first reset transistor (Fig. T5) is connected to a first clock signal terminal (Fig. 2; T5’s gate is connected to clock CK) or a third clock signal terminal, and a first electrode of the first reset transistor (Fig. 2; T5) is connected to the first node (Fig. 2; T5’s gate is connected to first Node N2 via Node N3 and T7); and
a control terminal of the turn-off unit (Fig. 2; T4) is connected to the first node (Fig. 2; Node 2) (Fig. 2; T4’s gate is connected to Node N2), a first terminal of the turn-off unit (Fig. 2; T4) is connected to a second electrode of the first reset transistor (Fig. 2; T5) and is configured to write a turn-on voltage into the second electrode of the first reset transistor (Fig. 2; T5) in response to the first node (Fig. 2; Node N2) controlling the turn-off unit to turn on ([0045]; the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.), and the turn-on voltage is a voltage for controlling the first output unit (Fig. 2; T3) to turn on ([0045]; an seventh transistor T7 is conducted, and the first clock control signal with the low level is transmitted to the second node N2 by the seventh transistor T7. For example, Vth7 represents a threshold voltage of the seventh transistor T7; Vth1 represents the threshold voltage of the first transistor T1; if Vth1<Vth7+Vth2, a voltage of the second node N2 is VL−Vth7−Vth2; and if Vth1>Vth7+Vth2, the voltage of the second node N2 is VL−Vth1. In this case, a third transistor T3 and a fourth transistor T4 are both conducted. Since the second clock control signal is a high level signal, a fifth transistor T5 is turned off.).
However, Feng does not explicitly disclose the first reset unit is configured to write a turn-off voltage into the first node, and the turn-off voltage is a voltage for controlling the first output unit to turn off.
In analogous art, Qing discloses the first reset unit is configured to write a turn-off voltage into the first node (Qing- Fig. 2; Node N2), and the turn-off voltage is a voltage for controlling the first output unit to turn off (Qing- Col. 13 lines 48-53, Fig. 2; The second transistor T2 transmits the first voltage signal to the second node N2, such that the voltage of the second node N2 is at a high level. The fourth transistor T4 is turned off under the control of the voltage of the second node N2, and the first voltage signal charges the third capacitor C3.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Qing to the system of Feng in order to provide a display with high contrast, low power consumption, extremely high reaction speed, light and thin, bendable and low cost.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0267881 hereinafter Feng) in view of Qing et al. (US 12,106,722 hereinafter Qing), and Sun et al. (US 2024/0355295 hereinafter Sun).
Referring to claim 17, Feng in view of Qing as applied above does not explicitly disclose further comprising a first clock signal line and a second clock signal line;
wherein the first clock signal line is electrically connected to a first clock signal terminal of an ith shift register and a second clock signal terminal of an (i+1)th shift register; and
the second clock signal line is electrically connected to a second clock signal terminal of the ith shift register and a first clock signal terminal of the (i+1)th shift register; wherein i is a positive integer.
In an analogous art, Sun discloses further comprising a first clock signal line and a second clock signal line (Fig. 3; CK2 and CK1 clock signals);
wherein the first clock signal line is electrically connected to a first clock signal terminal of an ith shift register and a second clock signal terminal of an (i+1)th shift register; and
the second clock signal line is electrically connected to a second clock signal terminal of the ith shift register and a first clock signal terminal of the (i+1)th shift register; wherein i is a positive integer ([0061]; As can be seen from the above discussion, the output terminal G in the circuit diagram (as the Nscan-type first gate driving unit 201) shown in FIG. 3 can be, but is not limited to, electrically connected to the gate of the first switching transistor T3 in the first pixel driving circuit 501 (see FIG. 4) of the corresponding stage (taking the n.sup.th stage as an example). And the gate of the second reset transistor T4 in the first pixel driving circuit 501 of the corresponding stage (taking the n.sup.th stage as an example) is electrically connected to the output terminal G of the (n+7).sup.th stage Nscan-type first gate driving unit 201. The Nscan-type first gate driving unit 201 in FIG. 3 may include a first clock signal line for transmitting the first clock signal CK1, a second clock signal line for transmitting the second clock signal CK2, and may further include a third input transistor M11, a fourth control transistor M12 to a third control transistor M20. Refer to FIG. 3 for the specific connection, loaded signals, and related electrical devices.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Sun to the system of Feng in view of Qing in order to reduce the power consumption of the driving module and to reduce the cost of the OLED dual-screen display.
Claim Objections
Claims 5-11 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 5, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the shift register further comprises an isolation transistor, a gate of the isolation transistor is connected to the first clock signal terminal, a first electrode of the isolation transistor is connected to the first node, and a second electrode of the isolation transistor and the control terminal of the first output unit are connected to a second node”.
Referring to claims 6-8 and 14-15 are objected upon dependent on the claim 5.
Referring to claim 9, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the first reset unit further comprises a second reset transistor, a gate of the second reset transistor is connected to the third node, a first electrode of the second reset transistor is connected to the second electrode of the first reset transistor, a second electrode of the second reset transistor is connected to a second power supply voltage terminal, and the second power supply voltage terminal provides the turn-off voltage”.
Referring to claim 10 is objected upon dependent on the claim 9.
Referring to claim 11, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the shift register comprises a second power supply voltage terminal for providing the turn-off voltage, the second power supply voltage terminal comprises a second power supply first sub-voltage terminal and a second power supply second sub-voltage terminal, and a voltage provided by the second power supply first sub-voltage terminal is greater than a voltage provided by the second power supply second sub-voltage terminal;
the second output unit comprises a third output transistor, a gate of the third output transistor is connected to the third node, a first electrode of the third output transistor is connected to the second power supply second sub-voltage terminal, and a second electrode of the third output transistor is connected to an output signal terminal; and
the shift register further comprises a third reset transistor, a gate of the third reset transistor is connected to the first node, a first electrode of the third reset transistor is connected to the third node, and a second electrode of the third reset transistor is connected to the second power supply second sub-voltage terminal”.
Referring to claim 16, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “further comprising a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein the first clock signal line is electrically connected to a first clock signal terminal of an ith shift register, a third clock signal terminal of an (i+2)th shift register and a second clock signal terminal of an (i+3)th shift register;
the second clock signal line is electrically connected to a second clock signal terminal of the ith shift register, a first clock signal terminal of an (i+1)th shift register, and a third clock signal terminal of the (i+3)th shift register;
the third clock signal line is electrically connected to a third clock signal terminal of the ith shift register, a second clock signal terminal of the (i+1)th shift register, and a first clock signal terminal of the (i+2)th shift register; and
the fourth clock signal line is electrically connected to a third clock signal terminal of the (i+1)th shift register, a second clock signal terminal of the (i+2)th shift register, and a first clock signal terminal of the (i+3)th shift register; wherein i is a positive integer”.
Conclusion
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/SCOTT D AU/Examiner, Art Unit 2624