DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7-8, 10, 16-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nuvoton Technology Corp (WO 2023/276799).
Regarding claim 1, Nuvoton disclosed a system in figures 1-3 that teaches: receiving at a first ADC (105), a first input signal to convert the first input signal to a first digital signal, receiving, at a second ADC (205), a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (The control circuit 20 also operates in a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate with the same gain", (see paragraph 0029); it is noted that the wording appears to indicate that the "controller" will receive the settings from the first ADC and send them to the second ADC, however the description is more clear in the matter. The controller will send the same settings to both ADCs, comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal "The error detection circuit 10 detects a measurement error based on the difference or ratio between two measurement results redundantly measured with the same gain by the first system and the second system. Therefore, the error detection circuit 10 includes a comparison circuit 11 and an error determination circuit 12 The comparison circuit 11 compares the output value of the first divider 106 and the output value of the second divider 206 and outputs an error. When the error output from the comparison circuit 11 exceeds the allowable value, the error determination circuit 12 determines that there is an error and outputs an error signal” (see paragraphs 0037-0039).
Regarding claim 7, Nuvoton further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 8, Nuvoton further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 10, claim 10 is similar to claim 1 in system format. Therefore, claim 10 is rejected as well as rejected in claim 1, such as: Nuvoton disclosed a system in figures 1-3 that teaches: receiving at a first ADC (105), a first input signal to convert the first input signal to a first digital signal, receiving, at a second ADC (205), a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (The control circuit 20 also operates in a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate with the same gain", (see paragraph 0029); it is noted that the wording appears to indicate that the "controller" will receive the settings from the first ADC and send them to the second ADC, however the description is more clear in the matter. The controller will send the same settings to both ADCs, comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal "The error detection circuit 10 detects a measurement error based on the difference or ratio between two measurement results redundantly measured with the same gain by the first system and the second system. Therefore, the error detection circuit 10 includes a comparison circuit 11 and an error determination circuit 12 The comparison circuit 11 compares the output value of the first divider 106 and the output value of the second divider 206 and outputs an error. When the error output from the comparison circuit 11 exceeds the allowable value, the error determination circuit 12 determines that there is an error and outputs an error signal” (see paragraphs 0037-0039).
Regarding claim 16, Nuvoton further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 17, Nuvoton further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 20, claim 20 is similar to claim 1 in system format. Therefore, claim 20 is rejected as well as rejected in claim 1, such as: Nuvoton disclosed a system in figures 1-3 that teaches: a first ADC to receive a first input signal and convert the first input signal to a first digital signal; a second ADC to obtain a second input signal and convert the second input signal to a second digital signal; a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC; and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal; wherein the computation logic circuitry is to perform an arithmetic operation on at least one of the first sample digital value from the first digital signal and a second sample digital value from the second digital signal, and compare a result of the arithmetic operation with one or more of a plurality of comparison thresholds.
Claims 1, 7-8, 10, 16-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motz et al. (US 2018/0247522).
Regarding claim 1, Motz discloses a system in figure 1 that teaches: receiving, at a first analog-to-digital converter (106-1) a first input signal to convert the first input signal to a first digital signal; receiving, at a second ADC (106-2) a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (given the vagueness, the clock frequency is a setting which is the same for each of the first and second ADC; paragraph (0049) discusses adapting the filter delay so the total processing chain delay, which can be considered as a setting is the same; comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal (see paragraph 0051).
Regarding claim 7, Motz further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 8, Motz further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 10, claim 10 is similar to claim 1 in system format. Therefore, claim 10 is rejected as well as rejected in claim 1, such as: Motz discloses a system in figure 1 that teaches: receiving, at a first analog-to-digital converter (106-1) a first input signal to convert the first input signal to a first digital signal; receiving, at a second ADC (106-2) a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (given the vagueness, the clock frequency is a setting which is the same for each of the first and second ADC; paragraph (0049) discusses adapting the filter delay so the total processing chain delay, which can be considered as a setting is the same; comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal (see paragraph 0051).
Regarding claim 16, Motz further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 17, Motz further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 20, claim 20 is similar to claim 1 in system format. Therefore, claim 20 is rejected as well as rejected in claim 1, such as: Motz discloses a system in figure 1 that teaches: a first ADC to receive a first input signal and convert the first input signal to a first digital signal; a second ADC to obtain a second input signal and convert the second input signal to a second digital signal; a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC; and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal; wherein the computation logic circuitry is to perform an arithmetic operation on at least one of the first sample digital value from the first digital signal and a second sample digital value from the second digital signal, and compare a result of the arithmetic operation with one or more of a plurality of comparison thresholds.
Claims 1, 7-8, 10, 16-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reuveni et al. (USP 6,567,022).
Regarding claim 1, Reuveni discloses a system in figure 1 that teaches: receiving, at a first analog-to-digital converter (106), a first input signal to convert the first input signal to a first digital signal; receiving, at a second ADC (108) a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (column 6, lines 1-6), discloses setting the gain of both ADC paths to the same setting), comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal (column 6, lines 9-15, the respective outputs of the ADCs are compared to each other and then the comparison is used to determine the gain difference due to mismatch).
Regarding claim 7, Reuveni further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 8, Reuveni further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 10, claim 10 is similar to claim 1 in system format. Therefore, claim 10 is rejected as well as rejected in claim 1, such as: Reuveni discloses a system in figure 1 that teaches: receiving, at a first analog-to-digital converter (106), a first input signal to convert the first input signal to a first digital signal; receiving, at a second ADC (108) a second input signal to convert the second input signal to a second digital signal; receiving one or more configuration settings of the first ADC and applying the one or more configuration settings to the second ADC (column 6, lines 1-6), discloses setting the gain of both ADC paths to the same setting), comparing, at a computation logic circuitry, the first digital signal and the second digital signal; and generating one or more computational results responsive to the comparing of the first digital signal and the second digital signal (column 6, lines 9-15, the respective outputs of the ADCs are compared to each other and then the comparison is used to determine the gain difference due to mismatch).
Regarding claim 16, Reuveni further teaches: receiving the first input signal and outputting the second input signal corresponding to a delayed version of the first input signal.
Regarding claim 17, Reuveni further teaches: the second input signal obtained by the second ADC is the same as the first input signal received by the first ADC.
Regarding claim 20, claim 20 is similar to claim 1 in system format. Therefore, claim 20 is rejected as well as rejected in claim 1, such as: Reuveni discloses a system in figure 1 that teaches: a first ADC to receive a first input signal and convert the first input signal to a first digital signal; a second ADC to obtain a second input signal and convert the second input signal to a second digital signal; a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC; and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal; wherein the computation logic circuitry is to perform an arithmetic operation on at least one of the first sample digital value from the first digital signal and a second sample digital value from the second digital signal, and compare a result of the arithmetic operation with one or more of a plurality of comparison thresholds.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: generating a first accumulated digital value by adding samples of the first digital signal; and generating a second accumulated digital value by adding samples of the second digital signal; wherein the comparing operation comprises comparing the first accumulated digital value and the second accumulated digital value with one or more of a plurality of comparison thresholds, wherein the plurality of comparison thresholds comprises an accumulated low comparison threshold and an accumulated high comparison threshold.
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: storing a first sample digital value of the first digital signal; and storing a second sample digital value of the second digital signal; wherein the comparing operation comprises comparing the first sample digital value and the second sample digital signal with one or more of the plurality of comparison thresholds, wherein the plurality of comparison thresholds comprises a sample low comparison threshold and a sample high comparison threshold.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the comparing operation comprises determining whether the first sample digital value and the second sample digital value fall within a sample range defined by the sample low comparison threshold and sample high comparison threshold, or whether the first accumulated digital value and the second accumulated digital value fall within an accumulated range defined by the accumulated low comparison threshold and accumulated high comparison threshold.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: triggering at least one of an interrupt signal for a processor of a microcontroller and one or more safety events in response to at least one of the first sample digital value and the second sample digital value falling outside the sample range, or at least one of the first accumulated digital value and the second accumulated digital value falling outside the accumulated range.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the comparing operation comprises performing an arithmetic operation on at least one of the first sample digital value, the second sample digital value, the first accumulated digital value, and the second accumulated digital value, and comparing a result of the arithmetic operation with one or more of the plurality of comparison thresholds; wherein the arithmetic operation is at least one of addition, subtraction, multiplication, division, averaging and scaling.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the comparing operation comprises comparing the first digital signal with the second digital signal and triggering at least one of an interrupt signal for a processor of a microcontroller and one or more safety events in response to determining that a difference between the first digital signal and the second digital signal exceeds one or more of a plurality of comparison thresholds.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: a first accumulator to generate a first accumulated digital value by adding samples of the first digital signal; a second accumulator to generate a second accumulated digital value by adding samples of the second digital signal; wherein the computation logic circuitry is to compare the first accumulated digital value and the second accumulated digital value with one or more of a plurality of comparison thresholds, wherein the plurality of comparison thresholds comprise an accumulated low comparison threshold and an accumulated high comparison threshold.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: a first sample register to store a first sample digital value of the first digital signal; and a second sample register to store a second sample digital value of the second digital signal; wherein the computation logic circuitry is to compare the first sample digital value and the second sample digital signal with one or more of the plurality of comparison thresholds, wherein the plurality of comparison thresholds comprises a sample low comparison threshold and a sample high comparison threshold.
Claim 13 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the computation logic circuitry is to determine whether the first sample digital value and the second sample digital value fall within a sample range defined by the sample low comparison threshold and sample high comparison threshold, or whether the first accumulated digital value and the second accumulated digital value fall within an accumulated range defined by the accumulated low comparison threshold and accumulated high comparison threshold.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the computation logic circuitry is to trigger at least one of an interrupt signal for a processor of a microcontroller and one or more safety events in response to at least one of the first sample digital value and the second sample digital value falling outside the sample range, or at least one of the first accumulated digital value and the second accumulated digital value falling outside the accumulated range.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the computation logic circuitry is to perform an arithmetic operation on at least one of the first sample digital value, the second sample digital value, the first accumulated digital value, and the second accumulated digital value, and compare a result of the arithmetic operation with one or more of the plurality of comparison thresholds; wherein the arithmetic operation is at least one of addition, subtraction, multiplication, division, averaging, and scaling.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the computation logic circuitry is to compare the first digital signal with the second digital signal, wherein the computation logic circuitry is to trigger at least one of an interrupt signal for a processor of a microcontroller and one or more safety events in response to determining that a difference between the first digital signal and the second digital signal exceeds one or more of a plurality of comparison thresholds.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to teach or suggest objected features, which is: wherein the computation logic circuitry comprises a window comparator low register to store a plurality of low comparison thresholds, and a window comparator high register to store a plurality of high comparison thresholds.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845
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