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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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The information disclosure statements (IDS) were filed with the application on 4/10/2025 and on 6/22/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 and 16-18 of U.S. Patent No. 12,302,025 (Chen). Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claims are either anticipated by, or would have been obvious over, the reference claims
Application 19/175657
Chen (US Patent #12,302,025)
1. A local ramp buffer, comprising:
a deep N- well layer disposed in a P- substrate beneath a surface of the P- substrate;
a P- well disposed between the surface of the P- substrate and the deep N- well layer;
an N- well structure disposed in the P- substrate and coupled to the deep N- well layer,
wherein the N- well structure is disposed between the surface of the P- substrate and the deep N- well layer,
wherein the P- well is disposed inside an opening in the N- well structure, and
wherein the N- well structure and the deep N- well layer are configured to isolate the P- well within the opening in the N- well structure between the surface of the P- substrate and the deep N- well layer; and
a source follower transistor disposed in the P- well, wherein the source follower transistor includes an N+ doped region in the P- well to provide a source terminal of the source follower transistor and a P+ doped region in the P- well to provide a body terminal of the source follower transistor,
wherein the source terminal is coupled to the body terminal and is configured to provide an output node of the local ramp buffer, and
wherein the source terminal and the body terminal are coupled to the N- well structure.
1. A local ramp buffer, comprising:
a deep N- well layer disposed in a P- substrate beneath a surface of the P- substrate;
a P- well disposed between the surface of the P- substrate and the deep N- well layer;
an N- well structure disposed in the P- substrate and coupled to the deep N- well layer,
wherein the N- well structure is disposed between the surface of the P- substrate and the deep N- well layer,
wherein the P- well is disposed inside an opening in the N- well structure, and
wherein the N- well structure and the deep N- well layer are configured to isolate the P- well within the opening in the N- well structure between the surface of the P- substrate and the deep N- well layer; and
a source follower transistor disposed in the P- well, wherein the source follower transistor includes a gate terminal coupled to the N- well structure and a ramp generator.
2. (Original) The local ramp buffer of claim 1,
wherein the source follower transistor further includes: a first N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor,
wherein the drain terminal is coupled to a power line;
a second N+ doped region in the P- well proximate to the gate terminal to provide a source terminal of the source follower transistor; and
a P+ doped region in the P- well to provide a body terminal of the source follower transistor,
wherein the source terminal is coupled to the body terminal and is configured to provide an output node of the local ramp buffer.
2. The local ramp buffer of claim 1, wherein the N+ doped region is a first N+ doped region, and wherein the source follower transistor further includes: a gate terminal proximate to the source terminal and coupled to a ramp generator; and a second N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line.
2. (Original) The local ramp buffer of claim 1,
wherein the source follower transistor further includes: a first N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor,
wherein the drain terminal is coupled to a power line;
a second N+ doped region in the P- well proximate to the gate terminal to provide a source terminal of the source follower transistor; and
a P+ doped region in the P- well to provide a body terminal of the source follower transistor,
wherein the source terminal is coupled to the body terminal and is configured to provide an output node of the local ramp buffer.
3. The local ramp buffer of claim 1, wherein a diode is formed at an interface between the N- well structure and the P- substrate, wherein an anode of the diode is coupled to ground through the P- substrate, and wherein a cathode of the diode is coupled to the body terminal and the source terminal of the source follower transistor.
3. (Original) The local ramp buffer of claim 2,
wherein a first diode is formed at a first interface between the N- well structure and the P- well, wherein an anode of the first diode is coupled to the body terminal and the source terminal, and wherein a cathode of the first diode is coupled to the gate terminal and the ramp generator.
4. (Original) The local ramp buffer of claim 2, wherein a second diode is formed at a second interface between the N- well structure and the P- substrate, wherein an anode of the second diode is coupled to ground through the P- substrate, and wherein a cathode of the second diode is coupled to the gate terminal and the ramp generator.
4. The local ramp buffer of claim 1, wherein the local ramp buffer is one of a plurality of local ramp buffers, each of the local ramp buffers including a corresponding (i) deep N-well layer, (ii) P- well, (iii) N- well, and (iv) source follower, wherein the deep N-well layer of each of the local ramp buffers is disposed in the P- substrate.
1. A local ramp buffer, comprising:
a deep N- well layer disposed in a P- substrate beneath a surface of the P- substrate;
a P- well disposed between the surface of the P- substrate and the deep N- well layer;
an N- well structure disposed in the P- substrate and coupled to the deep N- well layer,
wherein the N- well structure is disposed between the surface of the P- substrate and the deep N- well layer,
wherein the P- well is disposed inside an opening in the N- well structure, and
wherein the N- well structure and the deep N- well layer are configured to isolate the P- well within the opening in the N- well structure between the surface of the P- substrate and the deep N- well layer; and
a source follower transistor disposed in the P- well, wherein the source follower transistor includes a gate terminal coupled to the N- well structure and a ramp generator.
8. The local ramp buffer of claim 1, wherein: the N− well structure includes a plurality of openings; the plurality of openings include the opening; P− wells corresponding to a plurality of local ramp buffers are each disposed within a corresponding one of the plurality of openings in the N− well structure; and the plurality of local ramp buffers include the local ramp buffer.
5. The local ramp buffer of claim 4, wherein the (i) deep N-well layer, (ii) P- well, (iii) N- well, and (iv) source follower of each of the local ramp buffers are isolated from one another by the P- substrate.
9. The local ramp buffer of claim 8, wherein the N− well structure and the deep N− well layer are configured to isolate each of the P− wells within the corresponding one of the plurality of openings in the N− well structure.
6. The local ramp buffer of claim 1, further comprising a current source coupled between the output node of the local ramp buffer and ground.
5. (Original) The local ramp buffer of claim 2, further comprising a current source coupled between the output node and ground.
7. The local ramp buffer of claim 6, wherein the current source comprises: a first transistor having a gate terminal coupled to receive a current source bias voltage; and a cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, wherein the first transistor and the cascode transistor are coupled between the output node of the local ramp buffer and ground.
6. (Original) The local ramp buffer of claim 5, wherein the current source comprises: a first transistor, wherein a gate of the first transistor is coupled to receive a current source bias voltage; and a cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, and wherein the first transistor and the cascode transistor are coupled between the output node and ground.
8. The local ramp buffer of claim 7, wherein the current source further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.
7. (Original) The local ramp buffer of claim 6, wherein the current source further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.
9. A method for fabricating a plurality of local ramp buffers, the method comprising:
disposing a deep N- well layer in a P- substrate beneath a surface of the P- substrate;
disposing a plurality of N- well structures in the P- substrate and between the surface of the P- substrate and the deep N- well layer,
wherein each of the N- well structures defines an opening;
coupling the N- well structures to the deep N- well layer;
disposing a plurality of P- wells inside the openings of corresponding ones of the N- well structures,
wherein the deep N- well layer and the N- well structures are configured to isolate each of the P- wells within the opening of the corresponding N- well structure between the surface of the P- substrate and the deep N- well layer, and
wherein each of the P- wells corresponds to one of the plurality of local ramp buffers; and
disposing a plurality of source follower transistors in corresponding ones of the P- wells,
wherein a source terminal and a body terminal of each of the source follower transistors are (i) coupled together, (ii) configured to provide an output node of the corresponding local ramp buffer, and (iii) coupled to the corresponding N- well structure.
10. A method of fabricating a plurality of local ramp buffers, comprising:
disposing a deep N− well layer in a P− substrate beneath a surface of the P− substrate;
disposing an N− well structure with a plurality of openings in the P− substrate and between the surface of the P− substrate and the deep N− well layer;
coupling the N− well structure to the deep N− well layer;
disposing a plurality of P− wells inside the plurality of openings in the N− well structure,
wherein the N− well structure and the deep N− well layer are configured to isolate each of the plurality of P− wells within the plurality of openings in the N− well structure between the surface of the P− substrate and the deep N− well layer, and
wherein each of the plurality of P− wells corresponds to one of the plurality of local ramp buffers; and
disposing a plurality of source follower transistors in the plurality of P− wells,
wherein each of the plurality of source follower transistors includes a gate terminal coupled to the N− well structure and a ramp generator.
11. The method of claim 10, wherein each one of the plurality of P− wells is disposed in a respective one of the plurality of openings in the N− well structure.
10. The method of claim 9, wherein each of the source follower transistors includes an N+ doped region in the corresponding P- well to provide the source terminal of the source follower transistor and a P+ doped region in the corresponding P- well to provide the body terminal of the source follower transistor.
12. The method of claim 10, wherein each one of the plurality of source follower transistors is disposed in a respective one of the plurality of P− wells.
13. The method of claim 10, wherein each of the plurality of source follower transistors further includes: a first N+ doped region in one of the plurality of P− wells proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line; a second N+ doped region in the one of the plurality of P− wells proximate to the gate terminal to provide a source terminal of the source follower transistor; and a P+ doped region in the one of the plurality of P− wells to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and is configured to provide an output node of a respective local ramp buffer.
11. The method of claim 10, wherein the N+ doped region is a first N+ doped region, and wherein each of the source follower transistors further includes: a gate terminal proximate to the source terminal and coupled to a ramp generator; and a second N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line.
13. The method of claim 10, wherein each of the plurality of source follower transistors further includes: a first N+ doped region in one of the plurality of P− wells proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line; a second N+ doped region in the one of the plurality of P− wells proximate to the gate terminal to provide a source terminal of the source follower transistor; and a P+ doped region in the one of the plurality of P− wells to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and is configured to provide an output node of a respective local ramp buffer.
12. The method of claim 9, further comprising coupling a plurality of current sources between the output nodes of corresponding ones of the local ramp buffers and ground.
16. The method of claim 13, further comprising: for each of the plurality of local ramp buffers coupling a current source between the output node and ground.
13. The method of claim 12, wherein each of the current sources comprises: a first transistor having a gate terminal coupled to receive a current source bias voltage; and a cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, wherein the first transistor and the cascode transistor are coupled between the output node of the local ramp buffer and ground.
17. The method of claim 16, wherein the current source comprises: a first transistor, wherein a gate of the first transistor is coupled to receive a current source bias voltage; and a cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, and wherein the first transistor and the cascode transistor are coupled between the output node and ground.
14. The method of claim 13, wherein each of the current sources further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.
18. The method of claim 17, wherein the current source further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.
15. The method of claim 9, wherein, for each of the local ramp buffers: a diode is formed at an interface between the N- well structure and the P- substrate, an anode of the diode is coupled to ground through the P- substrate, and a cathode of the diode is coupled to the body terminal and the source terminal of the source follower transistor.
14. The method of claim 13, wherein for each of the plurality of local ramp buffers: a first diode is formed at a first interface between the N− well structure and the P− well of the respective local ramp buffer; an anode of the first diode is coupled to the body terminal and the source terminal; and a cathode of the first diode is coupled to the gate terminal and the ramp generator.
16. A readout circuit, comprising: a plurality of column circuits, each of the column circuits including one of a plurality of local ramp buffers, each of the local ramp buffers including: a deep N- well layer disposed in a shared P- substrate beneath a surface of the shared P- substrate; a P- well disposed between the surface of the shared P- substrate and the deep N- well layer; an N- well structure disposed in the shared P- substrate and coupled to the deep N- well layer, wherein the N- well structure is disposed between the surface of the shared P- substrate and the deep N- well layer, wherein the P- well is disposed inside an opening in the N- well structure, and wherein the N- well structure and the deep N- well layer are configured to isolate the P- well within the opening in the N- well structure between the surface of the shared P- substrate and the deep N- well layer; and a source follower transistor disposed in the P- well and having a source terminal and a body terminal, wherein the source terminal and the body terminal are (i) coupled together, (ii) configured to provide an output node of the local ramp buffer, and (iii) coupled to the N- well structure.
1. A local ramp buffer, comprising:
a deep N- well layer disposed in a P- substrate beneath a surface of the P- substrate;
a P- well disposed between the surface of the P- substrate and the deep N- well layer;
an N- well structure disposed in the P- substrate and coupled to the deep N- well layer,
wherein the N- well structure is disposed between the surface of the P- substrate and the deep N- well layer,
wherein the P- well is disposed inside an opening in the N- well structure, and
wherein the N- well structure and the deep N- well layer are configured to isolate the P- well within the opening in the N- well structure between the surface of the P- substrate and the deep N- well layer; and
a source follower transistor disposed in the P- well, wherein the source follower transistor includes a gate terminal coupled to the N- well structure and a ramp generator.
2. (Original) The local ramp buffer of claim 1,
wherein the source follower transistor further includes: a first N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor,
wherein the drain terminal is coupled to a power line;
a second N+ doped region in the P- well proximate to the gate terminal to provide a source terminal of the source follower transistor; and
a P+ doped region in the P- well to provide a body terminal of the source follower transistor,
wherein the source terminal is coupled to the body terminal and is configured to provide an output node of the local ramp buffer.
8. The local ramp buffer of claim 1, wherein: the N− well structure includes a plurality of openings; the plurality of openings include the opening; P− wells corresponding to a plurality of local ramp buffers are each disposed within a corresponding one of the plurality of openings in the N− well structure; and the plurality of local ramp buffers include the local ramp buffer.
17. The readout circuit of claim 16, wherein each source follower transistor includes an N+ doped region in the P- well to provide the source terminal of the source follower transistor and a P+ doped region in the P- well to provide the body terminal of the source follower transistor.
2. (Original) The local ramp buffer of claim 1,
wherein the source follower transistor further includes: a first N+ doped region in the P- well proximate to the gate terminal to provide a drain terminal of the source follower transistor,
wherein the drain terminal is coupled to a power line;
a second N+ doped region in the P- well proximate to the gate terminal to provide a source terminal of the source follower transistor; and
a P+ doped region in the P- well to provide a body terminal of the source follower transistor,
wherein the source terminal is coupled to the body terminal and is configured to provide an output node of the local ramp buffer.
Claims 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 8 of U.S. Patent No. 12,302,025 (Chen) in view of Kim (US Patent Pub. # 2020/0162067).
As to claim 19, Chen does not teach wherein each of the column circuits further includes one of a plurality of comparators, wherein each of the comparators includes a first input coupled to a pixel array and a second input coupled to the output node of the corresponding local ramp buffer. Kim (Fig. 3) teaches wherein each of the column circuits (ramp signal generator 30, comparison circuit 40, a counting circuit 50, a memory circuit 60, a control circuit 80, buffering circuit 90, and a column readout circuit 70) further includes one of a plurality of comparators (40), wherein each of the comparators (40) includes a first input coupled to a pixel array (pixel signal) and a second input coupled to the output node of the corresponding local ramp buffer (first buffer 91) (Para 75, 76, and 80).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a column circuits with comparators as taught by Kim to the readout circuit of Chen, to provide a comparator for limiting an output voltage swing thereof using an output voltage swing control block and a CIS including the same (Para 5 of Kim).
As to claim 20. Kim teaches further comprising a global ramp generator (global ramp generator) operably coupled to a gate terminal of each of the local ramp buffers (91) (Para 23).
Allowable Subject Matter
Claim18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/CHRISTOPHER K PETERSON/Primary Examiner, Art Unit 2637 8/21/2026
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