Prosecution Insights
Last updated: October 25, 2026
Application No. 19/175,770

SIGNAL TRANSMISSION DEVICE

Final Rejection §102§112
Filed
Apr 10, 2025
Priority
Sep 20, 2022 — JP 2022-149298 +1 more
Examiner
NGUYEN, LONG T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
854 granted / 955 resolved
+21.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
25 currently pending
Career history
985
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
19.1%
-20.9% vs TC avg
§102
37.2%
-2.8% vs TC avg
§112
33.0%
-7.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 955 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Terminal Disclaimer The terminal disclaimer filed on 08/07/26 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 12,298,787 has been reviewed and is accepted. The terminal disclaimer has been recorded. Specification The disclosure is objected to because of the following informalities: through-out the specification, the “in-phase signals” regarding the first and second input signals INP and INN, and regarding the first and second output signals OUTP and OUTN (see for example, paragraphs [0030]-[0031], [0033], [0046]-[0048], [0051], [0081]-[0082], [0115], [0116]-[0118], [0120], [0125]-[0126], [0128]-[0130], [0134]-[0135], [0138]-[0141], [0145], [0158]) should be changed to another term such as “common level signals” or “common-mode signals” because although the first and second input signals INP and INN have a common “LL signal”, and the first and second output signals OUTP and OUTN have a common “LL signal” (see Figure 3), however, the first and second input signals INP and INN, and the first and second output signals OUTP and OUTN are not aligned together, their peaks (Hi) and troughs (Lo) are not consistently happened at the exact same time (see Figure 3 which shows the input signals INP and INN are not consistently alignment, and the same for the output signals OUTP and OUTN). Clarification and/or appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the claim 1, the recitation “a pair of fixed in-phase signals of predetermined potentials” on line 2-3 appears to be misdescriptive because the disclosure disclose “a predetermined potential” (see [0051], and signals 1a-1b has a low potential during t2-t3). Further, the recitation “a reception buffer that outputs a pair of in-phase output signals” on line 5 appears to be misdescriptive because although the first and second output signals OUTP and OUTN have a common “LL signal” (see Figure 3), however the first and second output signals OUTP and OUTN are not aligned together, their peaks (Hi) and troughs (Lo) are not consistently happened at the exact same time (see Figure 3 which shows the output signals OUTP and OUTN are not consistently alignment when both inputs INP and INN are common Lo signals). Clarification and/or appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (USP 7,256,624). For claim 1, Figure 7 of Cheng et al. teaches an LVDS circuit comprising: a transmission buffer (204 Driver Buffer, wherein the Driver Buffer is shown in detail in Figure 10, also see Col. 11, lines 57-66) that outputs a pair of fixed in-phase signals (N4, N5) of predetermined potentials in response to input signals (BN, BP), when the input signals (BN, BP) are common-mode signals (in the operation of Driver Buffer in Figure 10, when input signals BN and BP are common signal Lo, the outputs N4 and N5 follows the inputs signals BN and BP, respectively; and when the input signals BN and BP are common signal Hi, the outputs N4 and N5 also follows the inputs signals BN and BP, respectively); and a reception buffer (206, Figure 7) that outputs a pair of in-phase output signals (TXP, TXN) in response to transmission signals (N4, N5) output from the transmission buffer (Driver Buffer, Figure 7) and input into the reception buffer (206, Figure 7), when the transmission signals (N4, N5) are the pair of fixed in- phase signals wherein the transmission buffer (Driver buffer 204, Figure 7) is provided in a first semiconductor chip (204, Figure 7), and the reception buffer (206, Figure 7) is provided in a second semiconductor chip (206, Figure 7) that is different from the first semiconductor chip (204, Figure 7). Response to Arguments Applicant's arguments filed 08/07/26 have been fully considered but they are not persuasive. It is noted that Applicant argues that Figure 6 of Cheng et al. does not output “a pair of in-phase output signals," in particular, "in response to transmission signals output from the transmission buffer and input into the reception buffer, when the transmission signals are the pair of fixed in-phase signals," as required by claim 1. However, this argument is not persuasive because, looking at different angle, Figure 7 of Cheng et al. now read on the amended claim 1 as discussed above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2836
Read full office action

Prosecution Timeline

Apr 10, 2025
Application Filed
May 07, 2026
Non-Final Rejection mailed — §102, §112
Aug 05, 2026
Examiner Interview Summary
Aug 05, 2026
Applicant Interview (Telephonic)
Aug 07, 2026
Response Filed
Oct 02, 2026
Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.2%)
1y 10m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 955 resolved cases by this examiner. Grant probability derived from career allowance rate.

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