Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12316310. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are either anticipated and/or obvious over the claims in view of Okashita in view of Lee further in view of AAPA.
Claim 2 recites the first-stage switch circuit further comprises: a first switch, coupled between the first common-mode node and the first input/output terminal; and a second switch, coupled between the first common-mode node and the first connection terminal of the first-stage switch circuit that is not recited in patent 12316310. Reference Okashita in view of Lee further in the view AAPA teaches [Okashita, fig. 11] the first-stage switch circuit further comprises: a first switch [Okashita, Snm, n=1, m=10], coupled between the first common-mode node [Okashita, IN-1] and the first input/output terminal [Okashita, IN-1 and OUT10]; and a second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], coupled between the first common-mode node [Okashita, IN-1] and the first connection terminal [Okashita, OUT10] of the first-stage switch circuit. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the first-stage switch circuit to include the first and second and second switches. The modification would be obvious because one of ordinary skill in the art would be motivated to improve switching usability by incorporating switches.
Claim 3 recites the first-stage switch circuit further comprises: a third switch, coupled between the first common-mode node and the second connection terminal of the first-stage switch circuit… two of the first switch, the second switch, and the third switch are turned on that is not recited in patent 12316310. Reference in view of Lee further in view of AAPA discloses teaches [Okashita, fig. 11] the first-stage switch circuit further comprises: a third switch [Okashita, S13 coupled between IN-1 and OUT2], coupled between the first common-mode node [Okashita, IN-1] and the second connection terminal [Okashita, OUT2] of the first-stage switch circuit, and two of the first switch [Okashita, S11], the second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], and the third switch [Okashita, S13] are turned on [Okashita, via nXm decoder, para. 52]. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the first-stage switch circuit to include the third switch and second and second switches and two of the first switch, the second switch, and the third switch are turned on. The modification would be obvious because one of ordinary skill in the art would be motivated to improve switching usability by including the third switch within the first stage circuitry and turning on of switches to improve usability and signal routing in a switching circuit.
Claim 4 recites each of the at least one second-stage switch circuit further comprises: a first switch, coupled between the second common-mode node and the second-stage transmission terminal; a second switch, coupled between the second common-mode node and the first connection terminal; and a third switch, coupled between the second common-mode node and the second connection terminal, and two of the first switch, the second switch, and the third switch are turned on that is not recited in patent 12316310. Reference Okashita in view of Lee further in view of AAPA teaches [Okashita, fig. 11] each of the at least one second-stage switch circuit [switches routing IN1 to OUT3, OUT4 and OUT8] further comprises: a first switch [Okashita, S11 or S12], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the second-stage transmission terminal [OUT1 and OUT2]; a second switch [Okashita, the other of S11 or S12], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the first connection terminal [Okashita, OUT1]; and a third switch, coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the second connection terminal [Okashita, OUT2], and two of the first switch [Okashita, S11], the second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], and the third switch [S13] are turned on [Lee, via nXm decoder, para. 52]. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the first-stage switch circuit to include the third switch and second and second switches and two of the first switch, the second switch, and the third switch are turned on. The modification would be obvious because one of ordinary skill in the art would be motivated to improve switching usability by including the third switch within the first stage circuitry and turning on of switches to improve usability and signal routing in a switching circuit.
Claim 5 recites each of the at least one second-stage switch circuit further comprises: a measurement port; and a fourth switch, coupled between the second common-mode node and the measurement port, wherein two of the first switch, the second switch, the third switch, and the fourth switch are turned on that is not recited in patent 12316310. Reference Okashita in view of Lee further in view of AAPA teaches each of the at least one second-stage switch circuit [Okashita, switches routing IN1 to OUT3, OUT4 and OUT8] further comprises: a measurement port [Lee, fig. 2, ADC1 accepting KEY_ADC]; and a fourth switch [Lee, a switch of the plurality of switches SW on outputs], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the port, wherein two of the first switch, the second switch, the third switch, and the fourth switch are turned on [switches turned on]. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the second-stage switch circuit to include a measurement port, a forth switch and two of the first, second, third and fourth switch are turned on. The modification would be obvious because one of ordinary skill in the art would be motivated to improve switching usability by including the measurement port, fourth switch and turning on of switches within the second to improve usability and signal routing in a switching circuit.
Claim 6 recites the measurement port is detachably connected to an external instrument that is not recited in patent 12316310. Reference Okashita in view of Lee further in view of AAPA teaches input unit 120 and controller 160 part of portable terminal 100 [Lee, fig. 1, para. 19]. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the multi-channel switch device to have the measurement port is detachably connected to an external instrument. The modification would be obvious because one of ordinary skill in the art would be motivated to improve switching usability by having a measurement port as being able to use differing devices so as to improve usability of a switching circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Okashita et al. (US 20080030255 A1 Okashita hereinafter.) in view of Lee et al. (US 20110102022 A1 and Lee hereinafter.), in view of Applicant Admitted Prior Art (Specification and Drawings; “AAPA”).
Regarding claim 1, Okashita discloses a multi-channel switch device [fig. 11, n-input m-output type Switch circuit], comprising: a first-switch circuit [S11, S12], comprising: a first common-mode node [IN-1]; a first input/output terminal [IN-1], configured to receive or output a high frequency signal [para. 4]; and at least one first-connection terminal [OUT1, OUT2]; at least one second-switch circuit [switches routing IN1 to OUT3, OUT4 and OUT8], each comprising: a second common-mode node [OUT1 and OUT2]; a second-transmission terminal [OUT1 and OUT2], coupled to a corresponding one of the at least one first-connection terminal [as shown in fig. 11]; and a plurality of second-connection terminals [OUT3 through OUT8]; a plurality of third-switch circuits [switches routing IN1 to OUT9 through OUT26], each comprising: a third common-mode node [OUT3 through OUT8]; a third-transmission terminal [OUT3 through OUT8], coupled to a corresponding one of the second-connection terminals [as shown in fig. 11]; and a second input/output terminal [OUT10], configured to output or receive the high frequency signal [IN-1 coupled to OUT10], wherein two of the first input/output terminal [IN-1 and OUT10] and the at least one first-connection terminal [OUT1, OUT2] are connected through the first common-mode node [IN-1 coupled to OUT10], wherein two of the second-transmission terminal [OUT1 and OUT2] and the second connection terminals [OUT3 through OUT8] are connected through the second common-mode node [OUT1 and OUT2 coupled to OUT3 through OUT8].
Okashita does not explicitly disclose the plurality of third-switch circuits comprising a reference terminal, coupled to a reference voltage through a load; Wherein two of the third-transmission terminal, the reference terminal, and the second input/output terminal are connected through the third common-mode node.
However, Lee discloses the plurality of third-switch circuits [fig. 3, sub-key row 230], each comprising a reference terminal [fig. 3, unlabeled ground terminal], coupled to a reference voltage [fig. 3, ground] through a load [R11 – R15]; wherein two of the third-transmission terminal, the reference terminal, and the second input/output terminal are connected through the third common-mode node [fig. 3, sub-key row 230 coupled to other sub key rows at common node coupled to Rp].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to include the switchable reference loads as taught by Lee onto outputs OUT3 through OUT8 of Okashita thereby improving impedance switching and signal routing within a switching circuit.
Okashita in view of Lee does not explicitly disclose staging in a multiple channel switching device.
However, fig. 1 and para. 2-4 of AAPA disclose a multi-channel switch device with staging. Therefore, it would have been obvious to one skilled in the art before the effective filing date to modify the teachings of Okashita in view of Lee to include the staging topology as taught by AAPA to improve functionality and usability of a multi-channel switching device.
Regarding claim 2, Okashit in view of Lee further in view of AAPA discloses further wherein: the at least one first-stage connection terminal [Okashita, fig. 11, OUT1, OUT2] comprises a first connection terminal [Okashita, OUT1], the first-stage switch circuit further comprises: a first switch [Okashita, Snm, n=1, m=10], coupled between the first common-mode node [Okashita, IN-1] and the first input/output terminal [Okashita, IN-1 and OUT10]; and a second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], coupled between the first common-mode node [Okashita, IN-1] and the first connection terminal [Okashita, OUT10] of the first-stage switch circuit.
Regarding claim 3, Okashita in view of Lee further in view of AAPA discloses further wherein: the at least one first-stage connection terminal [Okashita, fig. 11, OUT1, OUT2] further comprises a second connection terminal [OUT2], the first-stage switch circuit further comprises: a third switch [S13 coupled between IN-1 and OUT2], coupled between the first common-mode node [Okashita, IN-1] and the second connection terminal [OUT2] of the first-stage switch circuit, and two of the first switch [S11], the second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], and the third switch [S13] are turned on [via nXm decoder, para. 52].
Regarding claim 4, Okashita in view of Lee further in view of AAPA discloses further wherein: the at least one second-stage connection terminal [Okashita, OUT3 through OUT8] comprises a first connection terminal [Okashita, OUT3] and a second connection terminal [Okashita, OUT4], each of the at least one second-stage switch circuit [switches routing IN1 to OUT3, OUT4 and OUT8] further comprises: a first switch [Okashita, S11 or S12], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the second-stage transmission terminal [OUT1 and OUT2]; a second switch [the other of S11 or S12], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the first connection terminal [Okashita, OUT1]; and a third switch, coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the second connection terminal [Okashita, OUT2], and two of the first switch [Okashita, S11], the second switch [Okashita, any of the other switches, for example S13, S14…. S19 with a node coupled between IN-1 and OUT10], and the third switch [S13] are turned on [Lee, via nXm decoder, para. 52].
Regarding claim 5, Okashita in view of Lee further in view of AAPA discloses further wherein each of the at least one second-stage switch circuit [Okashita, switches routing IN1 to OUT3, OUT4 and OUT8] further comprises: a port [Lee, fig. 2, ADC1 accepting KEY_ADC]; and a fourth switch [Lee, a switch of the plurality of switches SW on outputs], coupled between the second common-mode node [Okashita, OUT1 and OUT2] and the port, wherein two of the first switch, the second switch, the third switch, and the fourth switch are turned on [switches turned on].
Okashita in view of Lee further in view of AAPA does not explicitly disclose the port as being a measurement port.
However, Lee discloses the switching nodes coupled to analog-to-digital converter input ADC1 input of controller 160 for use in communication and data transmission [fig. 2, para.20]. In analog to digital conversion, there is inherent measurement going on within the conversion process, for example the converter measuring an amplitude of an analog input to ensure accurate conversion to a digital signal. Without this measurement, the converter would not be able to accurately convert the signal. Therefore, it would have been obvious to one skilled in the art before the effective filing date include the measurement port as taught by Lee to ensure proper conversion of an analog to digital signal. Furthering this, applicant has provided no relevant improvement or requirement for a measurement port.
Regarding claim 6, Okashita in view of Lee further in view of AAPA does not explicitly disclose wherein the measurement port is detachably connected to an external instrument.
However, Lee shows input unit 120 and controller 160 part of portable terminal 100 [fig. 1, para. 19]. It would be obvious to one skilled in the art before the effective filing date to make the connection between input unit 120 and controller 160 as detachable to improve usability of a portable terminal. Furthering this, it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Eliassi (US 20200351219 A1) is cited to teach a switching matrix.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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