DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8 and 16 are objected to because of the following informalities:
As to claim 8, line 1, “clock recovery system” should be replaced with “clock recovery”.
As to claim 8, line 1, “n” in “n-way” should be defined in terms of range.
As to claim 16, line 1, “phase detection process” should be replaced with “phase detection”.
As to claim 16, line 2, “n” in “n-way” should be defined in terms of range.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (hereinafter referred to as “Hsieh”, US 2015/0180642) in view of Shvydun et al. (hereinafter referred to as “Shvydun”, US 2015/0234423).
As to claim 1, Hsieh teaches a system for a serializer/deserializer (SerDes) receiver (paragraphs [0002] and [0004]) operable to implement a first mode corresponding to a Mueller-Muller Phase Detection (MMPD) operation or a second mode corresponding to an Alexander Phase Detection (APD) operation, the first mode and the second mode configured for clock recovery (Fig. 4, MM CDR 472, Alexander CDR 438), the system comprising: an error slicer (Fig. 2, minor crossings, level P, paragraphs [0023] and [0041], claims 8, 11, and 12); and a phase detector configured to operate in the first mode corresponding to MMPD and the second mode corresponding to APD (Fig. 4, MM CDR 472, Alexander CDR 438, claims 8, 10, 11, and 12), wherein the phase detector is configured to adjust a phase of a recovered clock signal based on one or more error signals generated by the data slicer and/or the error slicer (Fig. 4, MM CDR 472, Alexander CDR 438, claims 8-12, paragraphs [0023], [0041], and [0042]).
Hsieh does not expressly teach a data slicer.
Shvydun further teaches a clock and data recovery system that comprises data slicer (that outputs sliced data, paragraph [0024], and error slicer Fig. 2, slicers 208, comparator 210, pattern LUT 212, output data, phase adjust signal, paragraph [0024]).
It would have been obvious to one of ordinary skill in the art to employ a data slicer in SerDes/CDR system to produce recovered data in a receiver that includes CDR (clock and data recovery) system.
As to claim 8, Hsieh does not expressly teach that the clock recovery system is adaptable to n-way interleaved architectures for phase detection.
Shvydunn further teaches a CDR system comprising 4-way time-interleaved architecture (Fig. 2, paragraph [0023]).
It would have been obvious to one of ordinary skill in the art to utilize an n-way interleaved architectures for phase detection in a CDR system in order to generate interleaving clock phases for time-interleaved track and hold circuit for phase detection.
Allowable Subject Matter
Claims 9-20 are allowed. Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Stojanovic et al., US 2019/0165926, Figs. 1-4, paragraph [0010]
Hsieh, US 8,396,110, abstract, Figs. 1-3
Momtaz, US 7,330,508, abstract, Figs. 1-6
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRESHTEH N AGHDAM whose telephone number is (571)272-6037. The examiner can normally be reached Monday-Friday 10:30-7:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRESHTEH N AGHDAM/Primary Examiner, Art Unit 2632
6/13/2026
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