DETAILED ACTION
Claims 1-9 and 19-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/10/2025 and 12/23/2025 is being considered by the examiner.
Election/Restrictions
Claim 3 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 19-20, previously withdrawn from consideration as a result of a restriction requirement, require all the limitations of a claim indicated as having allowable subject matter. Pursuant to the procedures set forth in MPEP § 821.04(a), the restriction requirement between inventions Species I and Species III, as set forth in the Office action mailed on 04/22/2026, is hereby withdrawn and claims 0 hereby rejoined and fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sela et al. (US2024/0143227) in view of Syu (US2011/0099323).
With respect claim 1, Sela et al. teaches a nonvolatile memory device configured to store data (see Fig. 1A and paragraphs 15 and 26; one or more non-volatile memory die 104);
a storage interface connected to an external host device (see Fig. 1C and paragraph 22; host systems 252 may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or fiber channel over Ethernet (FCoE) interface); and
a storage controller configured to receive a command from the external host device through the storage interface (see paragraphs 15, 17 and 36; Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die 104… host 300 generates the write commands) and to control the nonvolatile memory device in response to the command (see paragraph 17; non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device),
wherein, the storage controller receives a command sequence (see paragraph 34; sequence of commands are received and stored in queue), and the he command sequence includes a first write command instructing a first write operation, a second write command instructing a second write operation, and a flush command instructing a flush operation (see paragraph 34 and 43; command queue 500 stores WR CMD 1, WR CMD 2, and WR CMD 3, which are associated with Zones 3, 2, and 1, respectively. The command queue 600 also stores a Flush command that is associated with Zone 1. That is, the Flush command contains an identifier of the zone (here, Zone 1) of the data that the host 300 wants to flush).
Sela et al. does not teach wherein, when the storage controller receives a command sequence from the external host device more than a reference number of times, the storage controller executes the first write command by sequential write to store first write data in a first memory region of the nonvolatile memory device, and executes the second write command by random write to store second write data in a second memory region of the nonvolatile memory device.
However, Syu teaches wherein data is not stored in memory device until an enough/predetermined number of write commands are received (i.e., commands received more than a reference number of times) (see paragraph 19)… When a write command is received (step 32), the write data is written to the target zone depending on the type of write command. If the write command are a sequential access write command, the user data is written to a sequential data zone of the memory device (step 34) and sequential mapping data is generated and stored in the sequential write log; and if the write commands are a random access write command, the user data is written to a random data zone of the memory device (step 42) and random mapping data is generated and stored in the random write log(step 44) (see paragraph 22).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Sela et al. to include the above mentioned to improve performance of a non-volatile memory (see Syu, paragraphs 3, 17 and 20).
With respect claim 8, Sela et al. teaches wherein the storage controller is configured to store 2 or more bits of data in each of a plurality of first memory cells included in the first memory region, and store 1 bit of data in each of a plurality of second memory cells included in the second memory region (see paragraph 32; ache can be part of the non-volatile memory 104 (e.g., in single-level cell (SLC) blocks in the non-volatile memory 104). In this situation, “flushing the data to the non-volatile memory” can refer to copying the data stored in the cache portion of the non-volatile memory 104 to the longer-term portion of the non-volatile memory 104 (e.g., moving the data from the SLC blocks to the multi-level cell (MLC) blocks in the non-volatile memory 104)).
With respect claim 9, Sela et al. teaches a random access memory (RAM) device (see paragraph 32; sache can take any suitable form. For example, the cache can be volatile memory (e.g., RAM 116, which can be static random access memory (SRAM), dynamic random access memory (DRAM), etc.)), wherein the flush operation is an operation of moving data stored in the RAM device to the nonvolatile memory device (see paragraph 32; a cache, which can be used to initially store data received from the host 300 before the data is later sent (flushed) to the non-volatile memory 104 for storage).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sela et al. (US2024/0143227) and Syu (US2011/0099323) as applied to claim 1 above, and further in view of Singla et al. (US2025/0103205).
With respect claim 2, Sela et al. and Syu do not teach wherein capacity of the first write data is greater than capacity of the second write data.
However, Singla et al. teaches wherein it is determined if the data associated with Command 1 200 will exceed a first threshold and a second threshold. In an example, if it is predicted or determined that data associated with a received command will pass a first threshold but not a second threshold, the data may be written to random memory blocks instead of a sequential stream. If it is predicted or determined that data associated with the received command will exceed the first threshold and the second threshold, the data will be written to a sequential stream (see paragraphs 24-26).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Sela et al. and Syu to include the above mentioned to improve the overall performance of the data storage device (see Singla, paragraphs 4).
Allowable Subject Matter
Claims 19-20 are allowed.
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: No prior art or combination of prior art teaches or suggest wherein the first write data is snapshot data generated by a recall function activated in an operating system installed in the nonvolatile memory device and loaded into the external host device, and wherein the second write data is metadata as recited in claim 3; and activate a recall function of generating snapshot data and metadata obtained by capturing a screen displayed by an application executing on the host device, and transmit to the storage device a command sequence including a first write command instructing writing of the snapshot data and a second write command instructing writing of the metadata to the storage device, and wherein the storage controller is configured to: store the snapshot data in a first memory region of a system partition of the memory device by sequential write, and store the metadata in a second memory region of the system partition of the memory device by random write as recited in claim 19.
Park et al. (US2023/0273842) teaches wherein the processor is configured to, when the instructions are executed, generate a screenshot by capturing a screen output on the display module, determine metadata associated with the screenshot, and store the screenshot and the metadata in the memory, wherein the metadata may include a path configured to output the screen when the screenshot is captured (see Abstract).
However, Park et al. does not teach wherein the first write data is snapshot data generated by a recall function activated in an operating system installed in the nonvolatile memory device and loaded into the external host device, and wherein the second write data is metadata as recited in claim 3; and activate a recall function of generating snapshot data and metadata obtained by capturing a screen displayed by an application executing on the host device, and transmit to the storage device a command sequence including a first write command instructing writing of the snapshot data and a second write command instructing writing of the metadata to the storage device, and wherein the storage controller is configured to: store the snapshot data in a first memory region of a system partition of the memory device by sequential write, and store the metadata in a second memory region of the system partition of the memory device by random write as recited in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al. (US2022/0138096) teaches wherein controller stores data corresponding to a write request into a memory region of a random attribute or a memory region of a sequential attribute among the memory regions (see Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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