DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 18 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16, 18, and 19 of U.S. Patent No. 12,321,775. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the patented claims as seen in the mapping below.
Instant Application
12,321,775
Claim 18 A system, comprising: one or more peripheral devices configured to generate interrupt requests to cause respective interrupts to be serviced; one or more processor cores configured to service the interrupts; and a programmable interrupt controller configured to: receive the interrupt requests; track wait durations between arrival of the respective interrupt requests and the programmable interrupt controller transmitting respective interrupt requests to the one or more processor cores; determine whether the wait durations exceed respective wait thresholds indicated in one or more interrupt wait threshold registers; when the wait durations exceed the respective wait thresholds, determine a target core of the one or more processor cores for the respective interrupts with wait durations exceeding the respective wait thresholds; and transmit respective interrupt signals with wait durations exceeding the respective wait thresholds to respective target cores to cause the respective interrupts to be serviced by the respective target cores; and interrupt latency control circuitry configured to track a number of interrupt migrations of the respective interrupts over time and change a wait threshold of one or more respective interrupts based on the number of interrupt migrations.
Claim 16 A system, comprising: one or more peripheral devices configured to generate interrupt requests to cause respective interrupts to be serviced; one or more processor cores configured to service the interrupts; and a programmable interrupt controller configured to: receive the interrupt requests; track wait durations between arrival of the respective interrupt requests and the programmable interrupt controller transmitting respective interrupt requests to the one or more processor cores; determine whether the wait durations exceed respective wait thresholds indicated in one or more interrupt wait threshold registers; when the wait durations exceed the respective wait thresholds, determine a target core of the one or more processor cores for the respective interrupts with wait durations exceeding the respective wait thresholds; and transmit respective interrupt signals with wait durations exceeding the respective wait thresholds to respective target cores to cause the respective interrupts to be serviced by the respective target cores; and interrupt latency control circuitry configured to track a number of interrupt migrations of the respective interrupts over time and change an affinity or wait threshold of one or more respective interrupts based on the number of interrupt migrations.
19. The system of claim 18, wherein the interrupt latency control circuitry is configured to store a number of interrupt migrations for each respective interrupt.
18. The system of claim 16, wherein comprising interrupt latency control is configured to store the number of interrupt migrations for each respective interrupt.
20. The system of claim 19, where the interrupt latency control is configured to adjust an affinity of the respective interrupt based on the number of respective interrupt migrations.
19. The system of claim 18, where the interrupt latency control is configured to adjust the affinity of the respective interrupt based on the number of respective interrupt migrations.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 2, 9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Marietta et al. (US Publication Number 2014/0047149, hereinafter “Marietta”) in view of Madukkaraumukumana et al. (US Publication Number 2011/0161541, hereinafter “Madu”).
5. As per claims 1 and 14, Marietta teaches a system and method comprising: a plurality of processing cores (processor cores 141…141n, figure 3, paragraph 18); and an interrupt controller (interrupt controller, 114, figure 3, paragraph 18), comprising: an input terminal configured to receive an interrupt request (interrupt requests 130, figure 3); an interrupt controller timer (116, figure 3, paragraph 19); an output terminal configured to output an interrupt signal based on the interrupt request (asserted state interrupt handling, paragraphs 30 and 31)., wherein the interrupt signal is configured to cause a first processing core of the plurality of processing cores to service an interrupt corresponding to the interrupt signal (peripherals/external sources connected to the interface 124 via 128, figure 3, paragraph 19); interface configuration and status circuitry configured to track a period of time that the interrupt signal is transmitted to the first processing core(tracking wait for prioritization of the interrupts which maintains count of receive and processing times, paragraphs 21 and 22).
Marietta does not appear to explicitly disclose interrupt latency control configured to store a number of interrupt migrations for the interrupt and to adjust an affinity of the interrupt based on the number of interrupt migrations.
However, Madu discloses interrupt latency control configured to store a number of interrupt migrations for the interrupt and to adjust an affinity of the interrupt based on the number of interrupt migrations
Marietta and Madu are analogous art because they are from the same field of endeavor of interrupt handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Marietta and Madu before him or her, to modify the controller handling of Marietta to include the structure of Madu because it would enhance interrupt handling.
One of ordinary skill would be motivated to make such modification in order to enhance resource efficiency. Therefore, it would have been obvious to combine Madu with Marietta to obtain the invention as specified in the instant claim(s).
6. Marietta modified by the teachings of Madu as seen in claim 1 above, as per claim 2, Marietta teaches a system, wherein the interrupt controller comprises an interrupt wait threshold register that stores a wait threshold (special purpose threshold registers according to prioritization, paragraphs 23 and 24), wherein the interrupt controller is configured to compare the period of time to the wait threshold (the priority levels allow for handling based on wait thresholds from entering pending state to high priority state, paragraphs 30 and 40).
7. Marietta modified by the teachings of Madu as seen in claim 1 above, as per claim 9, Madu teaches a system, wherein the interrupt controller is configured to control at least one non-migratable interrupt that is not migratable between the plurality of processing cores (paragraphs 65 and 66).
8. Marietta modified by the teachings of Madu as seen in claim 1 above, as per claim 15, Marietta teaches a method, wherein the interrupt waits at the interrupt controller due to the core being busy servicing a higher priority interrupt thresholds (the priority levels allow for handling based on wait thresholds from entering pending state to high priority state, paragraphs 30 and 40).
Allowable Subject Matter
9. Claims 18 – 20 allowable upon addressing the double patenting rejection above.
Claims 3 – 8, 10 – 13, 16, and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Accapadi/Sun/Chen/Lee/Sabbineni/Shor have teachings of interrupt controller migration handling.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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