DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/10/2026 have been fully considered but they are not persuasive.
As per claim 1, Applicant argues that “In examining the feature "°an orthographic projection of the light-emitting control scanning signal line on the substrate is located at a side of an orthographic projection of a channel of the transmission transistor on the substrate away from an orthographic projection of a channel of the drive transistor on the substrate", the Examiner clearly interprets the phrase "away from an orthographic projection of a channel of the drive transistor on the substrate" as being in parallel with" located at a side of an orthographic projection of a channel of the transmission transistor on the substrate" to jointly define "an orthographic projection of the light-emitting control scanning signal line on the substrate". However, in fact, the phrase "away from an orthographic projection of a channel of the drive transistor on the substrate" is intended to further define "located at a side of an orthographic projection of a channel of the transmission transistor on the substrate". The Examiner's interpretation is erroneous.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant (implicitly) relies (i.e., “wherein a channel of the drive transistor is located at a greater distance from the light-emitting control scanning signal line than the channel of the transmission transistor is from said light-emitting control scanning signal line”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The Office respectfully submits that the previously cited Huang et al. teach wherein in a second direction (Fig. 6B, (negative) Y direction), an orthographic projection of the light-emitting control scanning signal line (Fig. 6B, EML/LY1) on the substrate is located at a side of an orthographic projection of a channel of the transmission transistor (Fig. 6B, T2, paragraph 119, “the channel of each transistor as well as the first electrode and the second electrode on both sides of the channel are located in the active layer LY0”; paragraph 103, “The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, and can form a channel region of the driving transistor T1, a channel region of the data writing transistor T2”, in other words, the light emitting control scanning line is located at a side of the channel of the transmission transistor) on the substrate away from an orthographic projection of a channel of the drive transistor (Fig. 6B, EML is located at a side of transistor T2 and it is also located away from transistor T1 in the (negative) Y direction) on the substrate, as claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10-14 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO2022174420 to Huang et al. For the purpose of the current Office Action, US 2023/0337465 will be used as an equivalent English translation.
As per claim 1, Huang et al. teach a display panel, comprising:
pixel sub-regions (Fig. 3, pixel units 100);
a substrate (Fig. 6E);
a light-emitting element (Fig. 6A, 100b) comprising a first electrode (Fig. 6A, E1), a light-emitting layer (Fig. 6E, function layer FL) and a second electrode (Fig. 6A, E2);
a pixel drive circuit (Fig. 6A, 100a) located at a side of the substrate (Figs. 3 and 6A, paragraph 50, “The display panel includes a pixel unit 100, and the pixel unit 100 is located on a base substrate … the pixel unit 100 includes a pixel circuit 100a”) and at least partially located in one of the pixel sub-regions (Fig. 3, paragraph 53, “an orthographic projection of the at least one first pixel circuit 10 on the base substrate BS at least partially overlaps with an orthographic projection of the at least one first light-emitting element 30”), wherein the pixel drive circuit comprises a drive transistor (Fig. 6A, T1), a light-emitting control transistor (Fig. 6A, T5), and a transmission transistor (Fig. 6A, T2), the drive transistor comprises a first electrode (Fig. 6A, T11) electrically connected to a first electrode (Fig. 6A, T22) of the transmission transistor and a second electrode (Fig. 6A, T12) electrically connected to a first electrode (Fig. 6A, T51) of the light-emitting control transistor, and a second electrode of the light-emitting control transistor (Fig. 6A, T52) is electrically connected to the first electrode of the light-emitting element (Fig. 6A, E1);
an adjustment control signal line (Fig. 6A, GT) extending in a first direction (paragraph 120, “As illustrated in FIG. 6B, …. the gate line GT …. extend along the first direction X”) and connected to a gate of the transmission transistor (Fig. 6A); and
a light-emitting control scanning signal line (Fig. 6A, EML) extending in the first direction (paragraph 120, “As illustrated in FIG. 6B … the light-emitting control signal line EML … extend along the first direction X”) and connected to a gate of the light-emitting control transistor (Fig. 6A);
wherein in a same pixel sub-region of the pixel sub-regions, in a second direction (Fig. 6B, (negative) Y direction), an orthographic projection of the light-emitting control scanning signal line (Fig. 6B, EML/LY1) on the substrate is located at a side of an orthographic projection of a channel of the transmission transistor (Fig. 6B, T2, paragraph 119, “the channel of each transistor as well as the first electrode and the second electrode on both sides of the channel are located in the active layer LY0”; paragraph 103, “The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, and can form a channel region of the driving transistor T1, a channel region of the data writing transistor T2” , in other words, the light emitting control scanning line is located at a side of the channel of the transmission transistor) on the substrate away from an orthographic projection of a channel of the drive transistor (Fig. 6B, EML is located at a side of transistor T2 and it is also located away from transistor T1 in the (negative) Y direction. Furthermore, The Office respectfully submits wherein the light-emitting control scanning signal line …. do not overlap the first semiconductor layer … between the second node N2 and the channel of the transmission transistor, and the first semiconductor layer …. between the second node N2 and the channel of the drive transistor, thus preventing a coupling impact on a voltage of the second node N2, such as disclosed in paragraph 39 of Applicant’s disclosure as filed) on the substrate; and the first direction intersects the second direction (Fig. 6B).
As per claim 2, Huang et al. teach the display panel according to claim 1, wherein in the same pixel sub-region, in the second direction, the orthographic projection of the channel of the transmission transistor (Fig. 6B, T2) on the substrate is located at a side of the orthographic projection of the light-emitting control scanning signal line (Fig. 6B, EML/LY1) on the substrate away from orthographic projection of the adjustment control signal line on the substrate (Fig. 6B, GT, both GT and T2 are located away from EML).
As per claim 10, Huang et al. teach the display panel according to claim 2, wherein the light-emitting control scanning signal line (Figs. 6A and 6B, EML) is reused as the gate of the light-emitting control transistor (Fig. 6A and 6B, T5).
As per claim 11, Huang et al. teach the display panel according to claim 1, wherein in the same pixel sub-region, in the second direction, the orthographic projection of the light-emitting control scanning signal line (Figs. 6A and 6B, EML) on the substrate is located at a side of an orthographic projection of a channel of the light-emitting control transistor (Figs. 6A and 6B, T5) on the substrate away from the orthographic projection of the channel of the drive transistor on the substrate (Figs. 6A and 6B, T1 and T5 are located away from each other).
As per claim 12, Huang et al. teach the display panel according to claim 11, wherein in a direction perpendicular to a plane of the substrate, a layer of the light-emitting control scanning signal line is located at a side of a layer of a gate of the drive transistor away from the substrate (Figs. 6A-6C, EML and the gate of T1 are located away from the substrate BS).
As per claim 13, Huang et all. teach the display panel according to claim 12, wherein the pixel drive circuit further comprises a storage capacitor (Fig. 6A, Cst), the storage capacitor comprises a first plate and a second plate, and the first plate is reused as the gate of the drive transistor (Fig. 6A, Ca shares the gate of the drive transistor T1); and in the direction perpendicular to the plane of the substrate, the first plate (Fig. 6C, Ca) is located between the substrate and the second plate (Fig. 6C, Cb); and the light-emitting control scanning signal line is disposed in a same layer as the second plate (Fig. 6C, Cb/LY1).
As per claim 14, Huang et al. teach the display panel according to claim 11, wherein in the same pixel sub-region, the orthographic projection of the light-emitting control scanning signal line (Figs. 6A and 6B, EML) on the substrate in the second direction is located at a side of an orthographic projection of the adjustment control signal line (Figs. 6A and 6B, GT) on the substrate away from the orthographic projection of the channel of the drive transistor on the substrate (Figs. 6A and 6B, T1 and GT are both located away from EML).
As per claim 20, Huang et al. teach a display apparatus (paragraph 146), comprising a display panel (Fig. 1), wherein the display panel comprises:
pixel sub-regions (Fig. 3, pixel units 100);
a substrate (Fig. 6E);
a light-emitting element (Fig. 6A, 100b) comprising a first electrode (Fig. 6A, E1), a light-emitting layer (Fig. 6E, function layer FL) and a second electrode (Fig. 6A, E2);
a pixel drive circuit (Fig. 6A, 100a) located at a side of the substrate (Figs. 3 and 6A, paragraph 50, “The display panel includes a pixel unit 100, and the pixel unit 100 is located on a base substrate … the pixel unit 100 includes a pixel circuit 100a”) and at least partially located in one of the pixel sub-regions (Fig. 3, paragraph 53, “an orthographic projection of the at least one first pixel circuit 10 on the base substrate BS at least partially overlaps with an orthographic projection of the at least one first light-emitting element 30”), wherein the pixel drive circuit comprises a drive transistor (Fig. 6A, T1), a light-emitting control transistor (Fig. 6A, T5), and a transmission transistor (Fig. 6A, T2), the drive transistor comprises a first electrode (Fig. 6A, T11) electrically connected to a first electrode (Fig. 6A, T22) of the transmission transistor and a second electrode (Fig. 6A, T12) electrically connected to a first electrode (Fig. 6A, T51) of the light-emitting control transistor, and a second electrode of the light-emitting control transistor (Fig. 6A, T52) is electrically connected to the first electrode of the light-emitting element (Fig. 6A, E1);
an adjustment control signal line (Fig. 6A, GT) extending in a first direction (paragraph 120, “As illustrated in FIG. 6B, …. the gate line GT …. extend along the first direction X”) and connected to a gate of the transmission transistor (Fig. 6A); and
a light-emitting control scanning signal line (Fig. 6A, EML) extending in the first direction (paragraph 120, “As illustrated in FIG. 6B … the light-emitting control signal line EML … extend along the first direction X”) and connected to a gate of the light-emitting control transistor (Fig. 6A);
wherein in a same pixel sub-region of the pixel sub-regions, in a second direction (Fig. 6B, Y direction), an orthographic projection of the light-emitting control scanning signal line (Fig. 6B, EML/LY1) on the substrate is located at a side of an orthographic projection of a channel of the transmission transistor (Fig. 6B, T2, paragraph 119, “the channel of each transistor as well as the first electrode and the second electrode on both sides of the channel are located in the active layer LY0”; paragraph 103, “The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, and can form a channel region of the driving transistor T1, a channel region of the data writing transistor T2”) on the substrate away from an orthographic projection of a channel of the drive transistor (Fig. 6B, EML is located at a side of transistor T2 and away from transistor T1 in the Y direction. Furthermore, The Office respectfully submits wherein the light-emitting control scanning signal line …. do not overlap the first semiconductor layer … between the second node N2 and the channel of the transmission transistor, and the first semiconductor layer …. between the second node N2 and the channel of the drive transistor, thus preventing a coupling impact on a voltage of the second node N2, such as disclosed in paragraph 39 of Applicant’s disclosure as filed) on the substrate; and the first direction intersects the second direction (Fig. 6B).
Allowable Subject Matter
Claims 3-9 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R SOTO LOPEZ whose telephone number is (571)270-5689. The examiner can normally be reached Monday-Friday, from 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571) 272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622
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