DETAILED ACTION
Response to Amendment
1. Applicant’s amendment filed on 09/29/26 has been received and entered in the case. The amendments to independent claims 1 and 13 do not distinguish patentably over the previously applied prior art, for the reasons set forth below.
Drawings
2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Note that the limitation in claim 2 that the first power-to-power clamp circuit includes a forward diode string is inconsistent with what is recited on the last five lines of claim 1, i.e., the last five lines of claim 1 recite the details of the first power to power clamp circuit shown in the embodiment of instant figure 7, but this embodiment does not include any forward diode string, i.e., there is no embodiment of applicant’s invention wherein the claimed first power-to-power clamp circuit comprises a switch coupled between the post driver voltage rail and the low-side logic-high voltage rail, and control circuitry configured to generate a control voltage to control the switch according to the overdrive voltage and the low-side operating voltage, and wherein the first power-to-power clamp circuit also includes a forward diode string including an anode coupled to the post driver voltage rail and a cathode coupled to the low-side logic-high voltage rail.
Claim Rejections - 35 USC § 112(a)
3. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2 and 16 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
As noted above, there is no embodiment of applicant’s invention wherein the claimed first power-to-power clamp circuit comprises a switch coupled between the post driver voltage rail and the low-side logic-high voltage rail, and control circuitry configured to generate a control voltage to control the switch according to the overdrive voltage and the low-side operating voltage, and wherein the first power-to-power clamp circuit also includes a forward diode string including an anode coupled to the post driver voltage rail and a cathode coupled to the low-side logic-high voltage rail.
Claim Rejections - 35 USC § 112(b)
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As noted above, the limitation in claim 2 that the first power-to-power clamp circuit includes a forward diode string is inconsistent with what is recited on the last five lines of claim 1, i.e., the last five lines of claim 1 recites the details of the first power to power clamp circuit shown in the embodiment of instant figure 7, but this embodiment does not include any forward diode string, and therefore claim 2 is misdescriptive of applicant’s invention. As noted above, there is no embodiment of applicant’s invention wherein the claimed first power-to-power clamp circuit comprises a switch coupled between the post driver voltage rail and the low-side logic-high voltage rail, and control circuitry configured to generate a control voltage to control the switch according to the overdrive voltage and the low-side operating voltage, and wherein the first power-to-power clamp circuit also includes a forward diode string including an anode coupled to the post driver voltage rail and a cathode coupled to the low-side logic-high voltage rail.
Claim 16 is indefinite for the same reason noted above in the rejection of claim 2, i.e., there is no embodiment in applicant’s invention wherein the first power-to-power clamp circuit includes the details recited on the last three lines of claim 13 and also includes a plurality of transistors and a plurality of serially connected diodes and a resistor and capacitor connected in series, as recited in claim 16.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bui (USP 7,589,584) in view of Davis et al (USPAP 2024/0372360) and further in view of Altolaguirre et al (USP 10,147,717).
As to claims 1 and 3, Bui discloses, in figure 2,
an electronic device comprising:
a post driver voltage rail (42) having an overdrive voltage (3.3V) greater than an operating voltage (1.8-3.3V) of an operating voltage rail (38); and
a low-side logic-high voltage rail (40) having a low-side operating voltage (2.5V) and coupled to a supply voltage rail (the claimed supply voltage rail reads on voltage rail 44, note that low-side logic-high voltage rail 40 is coupled to supply voltage rail 44 via circuit 32).
Not disclosed by Bui is the claimed first power-to-power clamp circuit recited on the last five lines of claim 1.
Davis et al discloses, in figure 2, a first power-to-power clamp circuit (255) coupled between a pair of power rails (260, 262) and Altiolaguirre et al discloses, in figure 2B, a clamp circuit coupled between a pair of power rails (V1 and V2), wherein the clamp circuit comprises a switch (160) and control circuitry (the combination of circuits 210 and 240) configured to generate a control voltage (the control voltage at a terminal T3) according to the voltage between power rails V1 and V2.
It would have been obvious to one of ordinary skill in the art to combine the above-noted teachings in Bui, Davis et al and Altolaguirre et al such that a first power-to-power clamp circuit is included between power rails 40 and 42 in Bui’s figure 2 where such a first power-to-power clamp circuit includes the circuitry shown in Altolaguirre et al’s figure 2B. The motivation for using a first power-to-power clamp circuit between voltage rails 40 and 42 in Bui’s figure 2 is to provide the well-known benefit associated with using such a power-to-power clamp circuit, i.e., providing protection to sensitive internal IC components from damage by limiting the voltage difference between such voltage rails during a high voltage ESD event, and the motivation for using a clamp circuit having the specific circuitry shown in figure 2B of Altolaguirre et al is to achieve the benefits disclosed in the abstract of this reference, i.e., good ESD robustness while maintaining low standby leakage current and a relatively small silicon footprint, and also note that when such an obvious first power-to-power clamp circuit is added to the Bui figure 2 circuitry, it will be configured to receive electrostatic discharge current between voltage rails 40 and 42, as recited on lines 7-9 of claim 1).
As to claim 2, as noted above this claim is indefinite because there is no embodiment in applicant’s invention where the first power-to-power clamp circuit includes a switch and control circuitry as recited on the last five lines of claim 1, and wherein the first power-to-power clamp circuit includes a forward diode string as recited in claim 2. However, to the extent that applicant simply means that the first power to power clamp circuit just includes a forward diode string instead of a switch and control circuitry, such does not distinguish patentably over Bui in view of Davis et al, the reason being that it was old and well-known in the art before the effective filing date of applicant’s invention that a power-to-power clamp circuit can include a forward diode string, each diode having its anode coupled to a higher voltage rail and its cathode coupled to a lower voltage rail, one example of this well-known concept being disclosed by Ker et al (USP 6,002,568), note the diode string formed by diodes 20a through 20d shown in figure 4 of this reference, and note that the motivation for one of ordinary skill in the art to use the above-noted obvious first power-to-power clamp circuit in Bui is to provide the benefit of having a bi-directional power-to-power clamp circuit, i.e., a clamp circuit which will provide ESD protection from potentially damaging voltage spikes passing from the higher voltage rail to the lower voltage rail or, alternatively, from the lower voltage rail to the higher voltage rail.
As to claim 4, although figure 2 of Bui does not disclose a first clamp circuit coupled between voltage rails 42 and 44, or a second clamp circuit coupled between voltage rails 40 and 44, it would have been obvious to one of ordinary skill in the art to add such clamp circuits into the Bui figure 2 circuitry, the motivation for such being to provide the benefit of preventing any of the voltage rails 40, 42 and 44 from receiving a damaging ESD spike which could be passed from one of the voltage rails to another of the voltage rails.
As to claim 5, the claimed first diode string including one or more diodes, each having an anode coupled to the low-side logic-high voltage rail and a cathode coupled to the post driver voltage rail, although not disclosed by Bui’s figure 2, would have been obvious for the reason noted above in the rejection of claim 2, i.e., it would have been obvious to use the power-to-power clamp circuitry shown in figure 4 of Ker et al to implement the above-noted obvious first power to power clamp circuit recited in independent claim 1, the motivation for using the Ker et al bi-directional ESD power to power clamp circuit in figure 2 of Bui is to achieve the above-noted benefit of having bi-directional ESD protection between voltage rails 40 and 42 in Bui, as noted above. Applicant should also note that the claimed one or more diodes recited on the second line of claim 5 can be read on diodes 22a when figure 2 of Bui is modified so as to include a power-to-power clamp circuit between voltage rails 40 and 42, wherein the structure of such a power-to-power clamp circuit includes bi-directional diodes 22a and 20a through 20d as shown in figure 4 of Ker et al.
As to claim 12, although figure 2 of Bui does not disclose a first power clamp circuit coupled between voltage rails 38 and 44, it would have been obvious to one of ordinary skill in the art to add such a first power clamp into the Bui figure 2 circuitry, the motivation for such being to provide the benefit of preventing either of voltage rails 38 and 44 from receiving a damaging ESD spike which could be passed from one voltage rail to the other voltage rail.
6. Claims 13, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bui, supra, in view of Davis et al, supra, and further in view of Ker et al (USP 6,002,568).
As to claims 13 and 15, Bui discloses, in figure 2,
an electrostatic discharge (ESD) protection circuit (just a statement of intended use, but note that when the above-noted ESD first power-to-power clamp circuit is obviously added to the Bui figure 2 circuitry, the modified Bui figure 2 circuitry will be an ESD protection circuit) comprising:
a first power clamp circuit coupled to a supply voltage rail (44) and a post driver voltage rail (42) having an overdrive voltage (the claimed overdrive voltage is 3.3V, and as noted above in the rejection of claim 4, it would have been obvious to one of ordinary skill in the art to add such a first power clamp circuit between voltage rails 42 and 44, the motivation for such being to provide the benefit of preventing damaging ESD voltage spikes from being passed from one voltage rail to the other, as noted above); and
a first power-to-power clamp circuit coupled to a low-side logic-high voltage rail and the post driver voltage rail (as noted above in the rejection of claim 1, it would have been obvious to one of ordinary skill in the art to add such a first power-to-power clamp circuit between voltage rails 40 and 42, the motivation for such being to provide the benefit of preventing damaging ESD voltage spikes from being passed from one voltage rail to the other, as noted above), the low side logic high voltage rail having a low side operating voltage (2.5V) lower than the overdrive voltage and coupled to a low voltage end of a core logic circuit (note that voltage rail 40 is coupled to a low voltage end of core logic circuit 30, i.e., either the 1.8 V supply input of core logic circuit 30 or the output terminal of core logic circuit 30 can be broadly interpreted as being a low-voltage end of core logic circuit 30), the first power to power clamp circuit configured to receive ESD current between the post driver voltage rail and the low-side logic-high voltage rail (when the above-noted first power-to-power clamp circuit is added to the Bui figure 2 circuitry, it will be configured to receive ESD current between voltage rails 40 and 42).
Not disclosed by figure 2 of Bui as modified above, i.e., modified so as to include a first power clamp circuit between voltage rails 42 and 44 and so as to include a first power to power clamp circuit between voltage rails 40 and 42, is that the first power-to-power clamp circuit comprises a plurality of serially connected diodes with an anode of each diode coupled to the post driver voltage rail and a cathode of each diode coupled to the low-side logic-high voltage rail.
Ker et al discloses, in figure 4, a first power-to-power clamp circuit (the power to power clamp circuit formed by the combination of diode 22a together with diodes 20a through 20d) coupled between a first voltage rail (VDDH) and a second voltage rail (VDDL) wherein the first power-to-power clamp circuit comprises a plurality of serially connected diodes (diodes 20a through 20d), with an anode of each diode coupled to the higher voltage rail (VDDH) and a cathode of each diode coupled to the lower voltage rail (VDDL).
It would have been obvious to one of ordinary skill in the art to form the above-noted obvious first power-to-power clamp circuit between voltage rails 40 and 42 in Bui’s figure 2 using the first power to power clamp circuit shown in figure 4 of Ker et al, the motivation for such being to provide the benefit of having a bi-directional power-to-power clamp circuit, i.e., a clamp circuit which will provide ESD protection from potentially damaging voltage spikes passing from the higher voltage rail to the lower voltage rail or, alternatively, from the lower voltage rail to the higher voltage rail.
As to claim 16, as noted above this claim is indefinite because there is no embodiment in applicant’s invention where the first power-to-power clamp circuit comprises a plurality of serially connected diodes with an anode of each diode coupled to the post driver voltage rail and a cathode of each diode coupled to the low-side logic-high voltage rail, as recited on the last three lines of claim 13, and wherein the first power to power clamp circuit also includes a plurality of transistors and a series connection of a resistor and capacitor, as recited in claim 16. However, to the extent that applicant intends claim 16 to recite that the first power-to-power clamp circuit just includes a plurality of transistors and a series connection of a resistor and capacitor, such does not distinguish patentably over figure 2 of Bui as modified by Davis et al, the reason being that performing a power-to-power clamp circuit as recited in claim 16 was known in the art prior to the effective filing date of applicant’s invention, note figure 2B of Altolaguirre et al as one example of such a power-to-power clamp circuit, the motivation for using the Altolaguirre et al power-to-power clamp circuit in figure 2 of Bui being to achieve the benefits disclosed in the abstract of this reference, i.e., good ESD robustness while maintaining low standby leakage current and a relatively small silicon footprint, as noted above.
Double Patenting
7. Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,301,219. Although the claims at issue are not identical, they are not patentably distinct from each other because, prior to applicant’s amendment, all of the limitations of claims 1-20 were anticipated by what is recited in the claims of the ‘219 patent, and all of the new limitations added to independent claims 1 and 13 in applicant’s amendment would have been obvious to one of ordinary skill in the art from what is disclosed by Davis et al, Altolaguirre et al and Ker et al, supra.
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Allowable Subject Matter
8. Claims 19 and 20 are allowed.
Claims 6-11, 14, 17 and 18 would be allowable upon the filing of the above-noted terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter: claims 6-11, 14 and 17-20 would be allowable upon the filing of the above-noted terminal disclaimer, for the reasons noted in paragraph six of the previous office action.
Prior Art Not Relied Upon
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The circuitry shown in figure 2 of Lacey et al (USP 6,384,628) is also seen to render obvious claims 1-5, 12, 13, 15 and 16 under 35 USC 103, using the same reasoning and analysis as set forth above in the rejections based on Bui’s figure 2, i.e., the claimed post driver voltage rail reads on the voltage rail receiving supply voltage VCCIO, the claimed low-side logic-high voltage rail reads on the voltage rail receiving supply voltage VCCINT, the claimed operating voltage rail reads on the voltage rail receiving supply voltage VCCIN, and the claimed supply voltage rail reads on the VSS voltage rail. Adding the claimed first power-to-power clamp circuit between VCCINT and VCCIO in figure 2 of Lacey et al would have been obvious to one of ordinary skill in the art in view of Davis et al, as noted above, and the claimed power clamp circuits between the various voltage rails in figure 2 of Lacey et al also would have been obvious to one of ordinary skill in the art, also for the reasons noted above.
Action is Final
10. Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 October 5, 2026
