DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on July 23, 2026.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on July 23, 2026 has been entered. Claims 6, 7 and 15-18 have been canceled. Claims 1-4, 8-13 and 19-20 are pending in the current application. Claims 1-4, 8-13 and 19-20 are rejected herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 8-13 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 19 and 20 recite “the RAID layer address spaces”. There is insufficient antecedent basis for “the RAID layer address spaces” in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-13 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Butterworth et al. (Hereinafter Butterworth, U.S. Patent No. 6,704,839).
Regarding claim 1, Butterworth teaches:
An input or output (IO) processing method, comprising:
acquiring IO data sent by a user by means of a logical volume (See Col. 6, lines 31-33 “When a host computer 102 issues a read or write request, the request is sent from the host computer to the controllers 108, 110 over a data bus 112.” See Col. 7, lines 26-29 “The controllers 200, 300 each have an uppermost layer 202, 302 which presents a set of logical devices or partitions, for example, partition A 204 and partition B 304 to the host computers.”), and sending, by means of a first controller determined by the logical volume, the IO data to a data cache (See Col. 4, lines 52-55 “Each controller may have a primary cache for the data from stripes designated to that controller and a secondary cache for data from stripes designated to another controller.” See Col. 7, lines 29-31 “Either controller 200, 300 may be accessed in order to perform a read or write operation of a partition 204, 304.” See Figure 2, in which Even Controller 200 (i.e. first controller) stores data in Cache 222 from logical devices/partitions 204/304), wherein the logical volume partitions a redundant array of independent disks (RAID) layer address space to a plurality of data blocks and selects data blocks from the plurality of data blocks to receive the IO data, the RAID layer address spaces refers to partitioning a corresponding address space for each controller at a RAID layer (See Claim 1 of Butterworth “A data storage system comprising at least two controllers and a storage device with data storage space which is shared by the controllers, wherein the controllers share the workload by dividing the shared storage space into n sets of stripes where the data storage space in one set of stripes is designated to one controller and each stripe is sufficiently small to divide the workload uniformly across the storage device, said at least two controllers comprising an interface for being coupled to at least one host for receiving read and write requests from the at least one host, said at least two controllers being communicatively coupled together for allocating amongst themselves received read and write requests in accordance with the set of stripes designated to each controller for executing the received read and write requests in a manner that is transparent to the at least one host.” See Abstract “This is achieved in the case of two controllers (200, 300) of a log structured array by dividing the storage space into odd and even tracks, all odd tracks being designated to one controller (300) and all even tracks to the other controller (200).” See Col. 4, line 6 “Each controller manages the data in its designated stripes.”. See Figure 2 in view of claim 1 of Butterworth and abstract, which depicts dividing/partitioning storage space amongst an even controller 200 and an odd controller 300, and performing data writes to each controller.), and the first controller is a controller configured for the data blocks that receives the IO data (See Col. 4, lines 52-55 “Each controller may have a primary cache for the data from stripes designated to that controller and a secondary cache for data from stripes designated to another controller.” See Col. 7, lines 29-31 “Either controller 200, 300 may be accessed in order to perform a read or write operation of a partition 204, 304.” See Figure 2, in which Even Controller 200 (i.e. first controller) stores data in Cache 222 from logical devices/partitions 204/304);
allocating a second controller to the IO data by means of a RAID (See Col. 4, lines 51-55 “Preferably, write operations are mirrored to the other, or at least one other, controller for redundancy. Each controller may have a primary cache for the data from stripes designated to that controller and a secondary cache for data from stripes designated to another controller.” See Col. 7, lines 49-54 “Even write tracks are even primary writes in the even controller 200 and these are passed 216 to the underlying layers of the even controller 200. The even write tracks are also mirrored 218 to the mirroring striping layer 310 of the odd controller 300 as even secondary writes which are passed 318 to the cache 322 of the odd controller 300.” See Col. 7, lines 62-67 “Odd write tracks are odd primary writes in the odd controller 300 and these are passed 316 to the underlying layers of the odd controller 300. The odd write tracks are also mirrored 318 to the mirroring striping layer 210 of even controller 200 as odd secondary writes which are passed 218 to the cache 222 of the even controller 200.” See Figure 2 which depicts multiple controllers dedicated to a RAID 5 configuration, in which writes are mirrored from even controller 200 to odd controller 300, then cached in cache 322. The Odd Controller 300 corresponds to the claimed second controller.), the second controller is configured for a target storage address space, and the target storage address space is selected from the RAID layer address spaces (See Claim 1 of Butterworth “A data storage system comprising at least two controllers and a storage device with data storage space which is shared by the controllers, wherein the controllers share the workload by dividing the shared storage space into n sets of stripes where the data storage space in one set of stripes is designated to one controller and each stripe is sufficiently small to divide the workload uniformly across the storage device, said at least two controllers comprising an interface for being coupled to at least one host for receiving read and write requests from the at least one host, said at least two controllers being communicatively coupled together for allocating amongst themselves received read and write requests in accordance with the set of stripes designated to each controller for executing the received read and write requests in a manner that is transparent to the at least one host.” See Abstract “This is achieved in the case of two controllers (200, 300) of a log structured array by dividing the storage space into odd and even tracks, all odd tracks being designated to one controller (300) and all even tracks to the other controller (200).” See Col. 4, line 6 “Each controller manages the data in its designated stripes.”. See Figure 2 in view of claim 1 of Butterworth and abstract, which depicts dividing/partitioning storage space amongst an even controller 200 and an odd controller 300, and performing data writes to each controller.);
in response to a determination that the IO data is a data write request, synchronizing the IO data from the first controller to the second controller by means of the data cache; and determining the target storage address space by means of the second controller, and performing a data write operation on the target storage address space based on the IO data (See Col. 4, lines 51-55 “Preferably, write operations are mirrored to the other, or at least one other, controller for redundancy. Each controller may have a primary cache for the data from stripes designated to that controller and a secondary cache for data from stripes designated to another controller.” See Col. 7, lines 49-54 “Even write tracks are even primary writes in the even controller 200 and these are passed 216 to the underlying layers of the even controller 200. The even write tracks are also mirrored 218 to the mirroring striping layer 310 of the odd controller 300 as even secondary writes which are passed 318 to the cache 322 of the odd controller 300.” See Col. 7, lines 62-67 “Odd write tracks are odd primary writes in the odd controller 300 and these are passed 316 to the underlying layers of the odd controller 300. The odd write tracks are also mirrored 318 to the mirroring striping layer 210 of even controller 200 as odd secondary writes which are passed 218 to the cache 222 of the even controller 200.” See Figure 2 which depicts multiple controllers dedicated to a RAID 5 configuration, in which writes are mirrored from even controller 200 to odd controller 300, then cached in cache 322. The Odd Controller 300 corresponds to the claimed second controller, and each controller has a cache that contains mirrored data from the cache of the other controller, and are thus synchronized.)
Claims 19 and 20 are rejected for the same reasons as claim 1.
Regarding claim 2, Butterworth teaches:
The IO processing method according to claim 1, wherein the partitioning a corresponding address space for each controller at a RAID layer comprises:
performing address space partitioning at the RAID layer in a unit of stripe according to an address partitioning rule, and assigning a unique controller to each group of address spaces (See Abstract “The controllers (200, 300) share the workload by dividing the shared storage space (244, 344) into stripes where the stripes are sufficiently small to divide the workload uniformly across the storage device. This is achieved in the case of two controllers (200, 300) of a log structured array by dividing the storage space into odd and even tracks, all odd tracks being designated to one controller (300) and all even tracks to the other controller (200).” See Figure 2 in view of abstract, which depicts dividing/partitioning storage space amongst an even controller 200 and an odd controller 300.).
Regarding claim 3, Butterworth teaches:
The IO processing method according to claim 1, further comprising:
partitioning, by means of the logical volume, a target unit-length space as a data block from an address space corresponding to a controller according to the RAID layer address space (See Col. 7, lines 26-29 “The controllers 200, 300 each have an uppermost layer 202, 302 which presents a set of logical devices or partitions, for example, partition A 204 and partition B 304 to the host computers.” See Abstract “The controllers (200, 300) share the workload by dividing the shared storage space (244, 344) into stripes where the stripes are sufficiently small to divide the workload uniformly across the storage device. This is achieved in the case of two controllers (200, 300) of a log structured array by dividing the storage space into odd and even tracks, all odd tracks being designated to one controller (300) and all even tracks to the other controller (200). See Col. 4, lines 34-45 “The data storage system optimally includes a processor and memory, and the data storage device is an array of storage devices having a plurality of data blocks organized on the storage devices in segments distributed across the storage devices,”), so as to obtain a plurality of data blocks corresponding to a plurality of controllers, wherein the plurality of data blocks are configured to receive the IO data written by a user into the logical volume (See Col. 4, lines 34-45 “The data storage system optimally includes a processor and memory, and the data storage device is an array of storage devices having a plurality of data blocks organized on the storage devices in segments distributed across the storage devices, wherein when a data block in a segment stored on the storage devices in a first location is updated, the updated data block is assigned to a different segment, written to a new storage location, and designated as a current data block, and the data block in the first location is designated as an old data block, ”).
Regarding claim 4, Butterworth teaches:
The IO processing method according to claim 1, wherein the allocating a second controller to the IO data by means of a RAID comprises:
selecting, by the RAID, a target storage address space from address spaces according to a current load condition of each address space; and
selecting a controller corresponding to the target storage address space as the second controller by querying the RAID layer address space (See Col. 4, lines 16-24 “According to a first aspect of the present invention there is provided a data storage system comprising at least two controllers and a storage device with data storage space which is shared by the controllers, wherein the controllers share the workload by dividing the shared storage space into n sets of stripes where the space in each set of stripes is designated to one controller and the stripes are sufficiently small to divide the workload uniformly across the storage device.” See Col. 4, lines 30-33 “In the case of two controllers, the shared storage space may be divided into stripes of odd and even tracks, all odd tracks being processed by one controller and all even tracks being processed by the other controller.” See Col. 4, lines 60-61 “Each controller may have a directory providing location information for data in stripes designated to that controller” See Claim 1 of Butterworth “said at least two controllers comprising an interface for being coupled to at least one host for receiving read and write requests from the at least one host, said at least two controllers being communicatively coupled together for allocating amongst themselves received read and write requests in accordance with the set of stripes designated to each controller for executing the received read and write requests in a manner that is transparent to the at least one host.” Under broadest reasonable interpretation, the address space may be searched/queried to locate the data/location that is to be updated/read in response to a write or read command.)
Regarding claim 9, Butterworth teaches:
The IO processing method according to claim 1, wherein the synchronizing the IO data from the first controller to the second controller comprises:
backing up the IO data stored in a cache region corresponding to the first controller to a cache region corresponding to the second controller (See Col. 4, lines 51-55 “Preferably, write operations are mirrored to the other, or at least one other, controller for redundancy. Each controller may have a primary cache for the data from stripes designated to that controller and a secondary cache for data from stripes designated to another controller.” See Col. 7, lines 49-54 “Even write tracks are even primary writes in the even controller 200 and these are passed 216 to the underlying layers of the even controller 200. The even write tracks are also mirrored 218 to the mirroring striping layer 310 of the odd controller 300 as even secondary writes which are passed 318 to the cache 322 of the odd controller 300.” See Col. 7, lines 62-67 “Odd write tracks are odd primary writes in the odd controller 300 and these are passed 316 to the underlying layers of the odd controller 300. The odd write tracks are also mirrored 318 to the mirroring striping layer 210 of even controller 200 as odd secondary writes which are passed 218 to the cache 222 of the even controller 200.”.).
Regarding claim 10, Butterworth teaches:
The IO processing method according to claim 1, wherein after the synchronizing the IO data from the first controller to the second controller by means of the data cache, the method further comprises:
generating synchronization node pair information corresponding to the IO data based on controller information of the first controller and the second controller, and storing the synchronization node pair information (See Col. 4 lines 60-61 “Each controller may have a directory providing location information for data in stripes designated to that controller.” See Col. 7, lines 39-41 “The mirroring striping layers 210, 310 divide read and write operations up into tracks and identifies odd and even tracks in the operation.”).
Regarding claim 11, Butterworth teaches:
The IO processing method according to claim 10, wherein after the storing the synchronization node pair information, the method further comprises:
notifying a corresponding controller to discard old cached data based on the synchronization node pair information when a cache is updated, and establishing new synchronization node pair information (See Col. 2, lines 30-39 “In an LSA, updated data is written into new logical block locations instead of being written in place. Large amounts of updated data are collected as tracks in controller memory and destaged together to a contiguous area of DASD address space called a segment. A segment is usually an integral number of stripes of a parity system such as RAID 5. As data is rewritten into new segments, the old location of the data in previously written segments becomes unreferenced. This unreferenced data is sometimes known as "garbage".” See Col. 2, lines 46-48 “To avoid this problem, a process known as "Free Space Collection" (FSC) or "Garbage Collection" must operate upon the old segments.”).
Regarding claim 12, Butterworth teaches:
The IO processing method according to claim 1, wherein the performing a data write operation on the target address space based on the IO data comprises:
judging whether any controller is reading data in the target address space (See Col. 7, lines 35-37 “All read and write requests are communicated in both of the controllers 200, 300 via paths 208, 308 to a mirroring striping layer 210, 310 in each controller 200, 300.”); and
in response to no controller reading data in the target address space, performing data flushing to the target address space based on the IO data (See Col. 8, lines 37-41 “In the case of the even controller 200, the even segment management component 232 processes even tracks which are destaged 228 from the even primary cache 224. The even writes are arranged in a new even segment which is written 238 to the DASDs.” See Col. 8, lines 53-57 “In the case of the odd controller 300, the odd segment management component 332 processes odd tracks which are destaged 328 from the odd primary cache 324. The odd writes are arranged in a new odd segment which is written 338 to the DASDS.”).
Regarding claim 13, Butterworth teaches:
The IO processing method according to claim 12, wherein after the judging whether any controller is reading data in the target address space, the method further comprises:
in response to a controller reading data in the target address space, detecting an accessed state of the target address space (See Col. 7, lines 35-37 “All read and write requests are communicated in both of the controllers 200, 300 via paths 208, 308 to a mirroring striping layer 210, 310 in each controller 200, 300.”); and
performing data flushing to the target address space based on the IO data in response to no controller reading data in the target address space (See Col. 8, lines 37-41 “In the case of the even controller 200, the even segment management component 232 processes even tracks which are destaged 228 from the even primary cache 224. The even writes are arranged in a new even segment which is written 238 to the DASDs.” See Col. 8, lines 53-57 “In the case of the odd controller 300, the odd segment management component 332 processes odd tracks which are destaged 328 from the odd primary cache 324. The odd writes are arranged in a new odd segment which is written 338 to the DASDS.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Butterworth in view of Yamaguchi et al. (Hereinafter Yamaguchi, U.S. Publication No. 2017/0262203).
Regarding claim 8, Butterworth teaches:
The IO processing method according to claim 1, wherein after the synchronizing the IO data from the first controller to the second controller by means of the data cache, the method further comprises:
generating a data write completion result (See Col. 3 lines 12-19 “Each storage controller processor typically comprises the following components. (a) An upstream communication channel to the host computer(s). (b) A non-volatile memory into which data written from the host computer may be stored between the time that completion status for the write is given to the host computer and the time that the data is committed to a DASD for long term storage.”), and
Butterworth does not explicitly disclose what Yamaguchi teaches:
sending a data backup completion result to the logical volume (See [0222] “Since the copy source and copy destination physical volumes 42 are both present in the storage apparatus 4, the copy processing successfully ends, the controller 41A sends a completion response to the copy controller 32A (Processing T61).”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data storage method of Butterworth with the data copy method of Yamaguchi to provide efficient communication during the data backup process, enabling the system to maintain accurate backup updates. Although Yamaguchi explicitly discloses the backup result to be sent to a controller, the combination of Butterworth and Yamaguchi would yield the backup result to be sent to the logical volume disclosed in Butterworth, as the storage system of Butterworth is comprised of logical devices that are part of the mirror process.
Response to Arguments
Applicant's arguments filed July 23, 2026 have been fully considered, and due to amendments filed on July 23, 2026, all previous rejections under 112(a) and 112(b) have been overcome. All pending claims in the instant application are rejected herein in view of prior art Butterworth and Yamaguchi.
Conclusion
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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