Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Priority
4. Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. § 119(a)–(d). A certified copy of KR 10-2024-0126094 has not been located in the file at the time of this Action; applicant is advised to confirm that the certified copy required by 37 CFR 1.55 has been filed. The effective filing date used for the prior-art analysis below is the September 13, 2024 foreign priority date, and each reference relied upon qualifies as prior art under that date.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-11 are rejected under 35 U.S.C. § 103 as being unpatentable over Severson et al. (“Severson”) (U.S. 8,447,007) in view of Turullols et al. (“Turullols”) (U.S. 8,990,606).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Severson and Turullols references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1. Severson teaches an electronic device comprising: a clock signal generation circuit configured to generate a first clock signal of a first period and a second clock signal of a second period, and to selectively output one of the first clock signal and the second clock signal (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Severson discloses dual-mode real-time counter apparatus integrated into a mobile phone, set-top box, computer, or fixed-location data unit (see claim 5; Abstract). Severson furthermore teaches fast clock signal and slow clock signal of different periods, with combinational logic providing glitch-free switching that selectively drives the counter from the fast or the slow clock (see Abstract; claims 1, 3: “gating off the fast clock signal … in response to the clock selection signal transitioning").
PNG
media_image1.png
1112
637
media_image1.png
Greyscale
a time count circuit configured to increase a time gray code in response to the first clock signal and decrease the time gray code in response to the second clock signal (in Severson, a real-time count is advanced per period of the fast clock and per period of the slow clock (see claim 1));
and a function circuit configured to generate a real-time value based on the time gray code (in Severson, counter output likewise is the real-time value. See Abstract, col. 3:59-67). Severson does not teach that the counted code is a gray code that INCREASES on the first (fast) clock and DECREASES on the second (slow) clock. In the same endeavor, Turullols teaches the counted code is a gray code that INCREASES on the first (fast) clock and DECREASES on the second (slow) clock (as shown in Fig. 4A, which is reproduced below for ease of reference and convenience, Turullols supplies a time gray code: a reference gray-code engine (472; two-bit gray code, col. 8; claim 8) whose value changes by only one bit per clock and from which a difference (subtractor 532) is computed; using a gray code guarantees no increment is missed when the clock period changes (col. 11-13: "the gray code guarantees that no increments … are missed"). The direction-encoding (increase on one clock / decrease on the other) is an obvious design choice given Turullols’s bidirectional delta computation (Table 2) and Severson’s two distinct per-period increments. Furthermore, Turullols teaches the timer-signal generating portion (counter latch 454 + adder 458/558) that increments a recursive/real-time timer signal 452 based on the gray-code-derived difference, producing a constant real-time value used by the system regardless of core-clock changes (Figs. 4A, 5B; col. 13-14).
PNG
media_image2.png
242
326
media_image2.png
Greyscale
Severson and Turullols are analogous art as both are real-time counters that must keep accurate time across two clock modes/frequencies for power savings in a processor. A person of ordinary skill in the art ("POSITA") before the effective filing date would have been motivated to implement Severson's per-period counter increments using Turullols's gray-code-based difference detection because Turullols expressly teaches that a gray code prevents the counter from being read at an invalid intermediate value (and thus prevents missed or erroneous increments) when the clock period changes (Turullols col. 11). The combination is the use of a known technique (gray-code counting, Turullols) to improve a similar device (Severson's dual-clock real-time counter) in the same way it improves other such counters that yielding the predictable result of a glitch-free, period-accurate real-time value across clock-mode transitions (KSR rationale (C)/(D); MPEP 2143). The modification requires only ordinary skill and produces predictable results.
In regard to claim 2, Severson teaches wherein the first period is shorter than the second period (Severson, teaches a fast clock (first, shorter period) and a slow clock (second, longer period). See Abstract: the fast/slow nomenclature establishes the shorter-vs-longer period relationship. Turullols similarly contemplates a reference clock faster than a slower core clock (col. 9; Fig. 4C)).
In regard to claim 3, (wherein the first, period is longer than the second period): the combination renders this obvious. Severson and Turullols both teach two clock signals of different periods that may be assigned in either order (Severson Abstract, fast/slow; Turullols col. 9-10, reference faster or slower than core - Figs. 4B vs. 4C expressly cover both the core-faster and core-slower cases). It would have been obvious to a POSITA to select whichever of the two period orderings suit the design, as each is one of only two possible arrangements of two clocks and Turullols expressly discloses both, yielding a predictable result (MPEP 2143, obvious to try / design choice among a finite set).
In regard to claim 4, (wherein the clock signal generation circuit is further configured to generate the first clock signal in a normal mode of the electronic device and generate the second clock signal in a sleep mode of the electronic device): the combination renders this obvious. Severson's fast/slow modes are power-management modes; Turullols generates the varying clock under dynamic voltage-frequency scaling (DVFS) power savings (col. 1-2). Substituting the express "normal mode / sleep mode" labels for Severson's fast/slow power modes is an obvious naming of the same power states.
In regard to claim 5, Severson teaches wherein the function circuit comprises a real-time value generation circuit that is configured to increase the real-time value by a first interval corresponding to the first period in response to an increase (in Severson, discloses that the counter output is increased by a FIRST counter increment for each period of the fast (first) clock (claim 1); this first increment corresponds to the first period). Severson does not expressly tie the increment to an INCREASE in a time GRAY code. Turullols supplies increasing the real-time timer by an amount (multiple of normalization value N) selected from the gray-code difference; when the gray code advances, the timer is incremented by the corresponding interval (Figs. 4A/5B; col. 12-13). Combining, the first interval = fast-clock period is added on each gray-code increase. A POSITA would add a period-scaled interval on each detected gray-code change to keep the accumulated real-time value equal to true elapsed time across the two clock periods - precisely the purpose of Severson's two per-period increments and Turullols's normalization multiples. Making the accumulated value always increase (adding the second-period interval even when the code direction reverses) is the predictable way to keep a monotonic elapsed-time value, and merely applies Severson's "increase by second increment for each slow-clock period" to Turullols's gray-code accumulator. Predictable result; ordinary skill (MPEP 2143(A),(C)).
In regard to claim 6, Severson teaches wherein the real-time value generation circuit is further configured to increase the real-time value by a second interval corresponding to the second period in response to a decrease (in Severson, discloses that the counter output is increased by a SECOND counter increment for each period of the slow (second) clock (see claim 1) - the second interval corresponds to the second period). Severson does not tie the second increment to a DECREASE in the time gray code. Turullols supplies difference-based selection of the increment magnitude from the (bidirectional) gray-code delta (Figure 5: subtractor 532, Table 2 covers wrap/decrease cases; multiplexer selects +N, +2N, +3N). Assigning the second-period interval to the decrease-direction event is obvious given Severson’s second per-period increment and Turullols’s direction-aware delta. A POSITA would add a period-scaled interval on each detected gray-code change to keep the accumulated real-time value equal to true elapsed time across the two clock periods - precisely the purpose of Severson's two per-period increments and Turullols's normalization multiples. Making the accumulated value always increase (adding the second-period interval even when the code direction reverses) is the predictable way to keep a monotonic elapsed-time value, and merely applies Severson's "increase by second increment for each slow-clock period" to Turullols's gray-code accumulator. Predictable result; ordinary skill (MPEP 2143(A),(C)).
In regard to claim 7, Turullols teaches wherein the function circuit comprises a real-time value generation circuit which comprises: a code conversion circuit configured to receive the time gray code and to convert the time gray code into a time binary code (in Turullols’s decoding unit (526), which receives the gray-code bits and decodes them into a binary value (col. 14; Table 1 maps gray bits [Wingdings font/0xE0] binary value); the gray-code engine 470/515 supplies the time gray code); a difference detection circuit configured to detect a change in the time gray code and to generate a difference signal depending on the change in the time gray code (in Turullols’s subtractor/logic unit (532/422), which computes the difference (delta) between the current gray-code value and the previous value and outputs that calculated difference as the multiplexer-control (difference) signal (cols. 11-14; Table 2); and a time value generation circuit configured to change the real-time value based on the difference signal (in Turullols’s counter portion (450) - multiplexer 540 + adder 558 + counter latch 560 - which changes the real-time timer signal 452/562 by the multiple of N selected by the difference signal (col. 14-15; Fig. 5B), wherein a magnitude of a value indicated by the time binary code is identical to a magnitude of a value indicated by the time gray code (in because Turullols’s decode unit converts the gray code to the equivalent binary value (Table 1: gray 11 [Wingdings font/0xE0] binary value 2, etc.) - the same magnitude), and wherein the time value generation circuit is further configured to increase the real-time value by a second interval corresponding to the second period in response to the difference signal generated by the difference detection circuit indicating a decrease in the time gray code (in Turullols’s multiplexer selects a larger increment (+2N/+3N) accounting for the interval, and the accumulator increases the timer accordingly (see col. 14). Severson supplies increasing the counter by a second increment corresponding to the second (slow) clock period (see claim 1); assigning that second-period increment to the decrease-direction difference is obvious. Severson and Turullols are analogous real-time-counter art. As in the rejection of claims 1-2 above, Severson's dual-clock real-time counter remains the base device, modified to use Turullols's gray-code-based difference-and-accumulation architecture; that architecture already accumulates period-scaled increments from the gray-code difference. Incorporating Severson's express “second increment for each slow-clock period” so that a decrease-direction change adds the second-period interval keeps the accumulated value equal to true elapsed time across both clock periods. This is a combination of known elements per known methods yielding a predictable result (MPEP 2143(A)); a POSITA would be motivated by the shared goal of an error-free real-time value across clock-mode changes.
In regard to claim 8, Turullols teaches wherein the real-time value generation circuit further comprises a delay circuit configured to generate a delayed time binary code by delaying the time binary code, wherein the delay circuit is further configured to provide the delayed time binary code to the difference detection circuit, and wherein the difference detection circuit is further configured to detect a change in the time binary code based on a comparison between the time binary code and the delayed time binary code (in Turullols discloses a delay latch (320/420/534) that delays the decoded value by one core-clock cycle and provides the delayed value to the second input of the subtractor/logic unit, which detects the change by comparing the current value to the delayed (previous) value (see col. 14; Fig. 5A - delay latch 534 [Wingdings font/0xE0] second input 536 of subtractor 532)). Obvious for the reasons above.
In regard to claim 9, Turullols teaches wherein the time value generation circuit is further configured to increase the real-time value by a first interval corresponding to the first period in response to the difference signal generated by the difference detection circuit indicating an increase in the time gray code (in Turullols increments the timer by +N (first interval) when the delta indicates one increment (col. 12/14; multiplexer input 464/546 = +N). Severson ties the first increment to the first (fast) period (see claim 1)). Obvious for the reasons above.
In regard to claim 10, Turullols teaches wherein the time value generation circuit further comprises a time value register configured to store the real-time value (in Turullols's counter latch (454/560) is a register that stores the real-time timer value and feeds it back for accumulation (see Fig. 5B; col. 14)). Obvious for the reasons above.
In regard to claim 11, (wherein the time count circuit is further configured to receive a mode signal indicating a mode of the electronic device, and determine whether to output the first clock signal or the second clock signal based on the mode signal): the combination renders this obvious. Severson teaches a clock-selection signal that indicates the fast or slow clock mode and governs which clock advances the counter (claim 1: "in response to the clock select signal indicating the fast clock mode … otherwise …"). Determining the clock/count behavior from that mode-indicating select signal reads on claim 11. Turullols's DVFS mode likewise selects the operative clock. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to route Severson's mode/clock-select signal to the time-count logic to determine the counting direction/clock, for the predictable benefit of correct mode-dependent counting.
7. Claims 12-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Turullols in view of Severson.
In regard to claim 12, Turullols teaches a real-time value generation device configured to generate a real-time value, the real-time value generation device comprising: a code conversion circuit configured to convert a time gray code comprising a plurality of bits into a time binary code (as shown in Fig. 5A, which is reproduced below for ease of reference and convenience, Turullols discloses the code unit 526, which converts the multi-bit gray code (515) into a binary value (col. 14; Table 1));
PNG
media_image3.png
582
421
media_image3.png
Greyscale
a difference detection circuit configured to generate an increase event signal in response to detecting an increase in the time gray code, and a decrease event signal in response to detecting a decrease in the time gray code (in Turullols’s subtractor 532 detects the direction/magnitude of change of the gray code (Table 2 includes both increase and wrap/decrease deltas) and outputs the difference signal used to select the increment). See col. 14-15);
a decrease event count circuit configured to identify a number of decrease events indicating a number of times the time gray code decreases, according to the decrease event signal (in Turullols’s accumulator, which counts/sums the selected increments over time (counter latch 560 + adder 558); counting the number of decrease-direction events is an obvious counting of Turullols’s decrease-direction deltas. Severson’s counter is advanced once per slow-clock period (see claim 1, col. 15-16) - i.e., counting slow-period (decrease-mode) events);
and an accumulation circuit configured to generate the real-time value based on the number of decrease events (in Turullols’s adder 558/counter latch 560, which accumulate the increments to generate the real-time timer value (see Fig. 5B, col. 15-16), wherein the time gray code increases in response to a first clock signal of a first period, and decreases in response to a second clock signal of a second period (in Turullols’s gray code is paced by a reference clock (see col. 8). Assigning increase to the first clock and decrease to the second is obvious given the bidirectional delta and Severson’s two per-period increments). But Turullols does not label separate ‘increase event’ and ‘decrease event’ signals for a code that both rises and falls. In the same field of endeavor, Severson supplies the two-direction/two-period paradigm (increment per fast period AND per slow period, claim 1). Generating distinct increase/decrease event signals from Turullols’s bidirectional delta is an obvious implementation (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Severson discloses the count that is advanced per fast (first) period and per slow (second) period (see Abstract, claim 1)).
PNG
media_image4.png
344
601
media_image4.png
Greyscale
Turullols's gray-code accumulator combined with Severson's per-period, two-mode increments predictably yields a real-time value computed from the number of decrease (slow-clock) events and increase (fast-clock) events. A POSITA seeking an error-free real-time value across clock modes would count the events in each direction and accumulate the corresponding period intervals (MPEP 2143(A),(C)).
In regard to claims 13-14, 19, wherein the first period is shorter than the second period and wherein the first period is longer than the second period: Severson and Turullols both teach two clock signals of different periods that may be assigned in either order (Severson Abstract, fast/slow; Turullols col. 9, reference faster or slower than core - Figs. 4B vs. 4C expressly cover both the core-faster and core-slower cases). It would have been obvious to a POSITA to select whichever of the two period orderings suit the design, as each is one of only two possible arrangements of two clocks and Turullols expressly discloses both, yielding a predictable result (MPEP 2143, obvious to try / design choice among a finite set).
In regard to claim 15, (further comprising an increase event count circuit configured to identify a number of increase events indicating a number of times the time gray code increases, according to the increase event signal, wherein the accumulation circuit is further configured to generate the real-time value based on the number of increase events): symmetric to claim 12's decrease-event limitation; Turullols's accumulator sums increase-direction increments (see col. 12-14) and Severson counts fast-period increments (see claim 1). Obvious for the same reasons.
In regard to claims 16, 20, Turullols teaches wherein the accumulation circuit is further configured to generate the real-time value by adding a first real-time value generated based on the number of decrease events and a second real-time value generated based on the number of increase events (Turullols’s accumulator adds increments derived from both directions of gray-code change into a single timer value (adder 558; see col. 14-16); generating a first sub-value from increase events and a second sub-value from decrease events and adding them is an obvious partition of Turullols’s accumulation. Severson’s real-time value is formed from fast-period increments plus slow-period increments (see claim 1),
and wherein the real-time value generation device further comprises a time interval multiplying circuit configured to generate a converted number of decrease events based on a product of the number of decrease events and a coefficient corresponding to the second period (Turullols’s each multiplexer input is a multiple (×2, ×3 via multiplier 550 / adder 552) of the normalization value N - i.e., a product of a count and a coefficient corresponding to a clock period (col. 14; Fig. 5B, +2N/+3N inputs). Turullols’s multiplier scales by a fixed set of multiples rather than by a ‘coefficient corresponding to the second period’ applied to a counted number of decrease events. However Severson supplies the second-period increment magnitude (second counter increment per slow-clock period, claim 1); multiplying the number of slow-period (decrease) events by that second-period coefficient to convert them to first-period-equivalent units is obvious in view of Severson’s per-period increments and Turullols’s multiplier structure. A POSITA would scale the count of slow-clock (decrease) events by the ratio of the second period to the first period so that decrease events and increase events can be summed in common time units, producing a correct elapsed-time value — the express purpose of Severson's second per-period increment and Turullols's normalization multiples. Using a multiplier to apply a period-based coefficient is a known technique (Turullols's ×N multiplier) applied to Severson's slow-period increment for the predictable result of unit-consistent accumulation (MPEP 2143(A),(C)).
In regard to claim 17, Turullols teaches wherein a minimum change amount of the number of increase events corresponds to the first period, and wherein a minimum change amount of the converted number of decrease events corresponds to the second period: this is the natural consequence of the claim 16 scaling - the increase-event count resolves in first-period units and the converted decrease-event count resolves in second-period units. Turullols's normalization value N sets the minimum increment/resolution (see col. 12/14) and Severson ties each increment to a clock period (see claim 1). Obvious for the reasons stated for claims 12 and 16.
Claim 18 (method) recites the same operative limitations as device claim 12. The change in claim format from device to method does not confer patentability where the underlying operations are identical to those taught by the applied references. See MPEP § 2114; In re Bernhart, 417 F.2d 1395 (CCPA 1969). The element-by-element mapping set forth for claim 12 applies with equal force to claim 18.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
8. All claims are rejected.
9. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Nakamura et al., U.S. Patent No. 6,907,098, teach gray counter using gray[Wingdings font/0xE0]binary conversion, logical operation, and binary[Wingdings font/0xE0]gray reconversion; pertinent to the code-conversion/accumulation architecture of claims 7, 12.
Neidengard et al., U.S. Patent No. 10,439,617, teach sequential logic + increment/decrement logic maintaining gray-code format throughout; pertinent to the increase/decrease of the time gray code (claims 1, 12).
Kim et al., U.S. Patent No. 10,419,003, teach gray-code generator selectable between higher- and lower-frequency clocks for low-power operation; pertinent to claims 1-4 clock-selection.
Zak et al., U.S. Patent No. 5,818,847, teach real-time-clock increment with normal vs. error-compensation modes and cumulative value; pertinent to claims 5–6/12 accumulation.
Flatner et al., U.S. Patent Pub. No. 2005/0097228, teach performance counter accumulating a variable increment value that varies with processor clock frequency; pertinent to the period-scaled increment of claims 5–6, 16.
Hall et al., EP 0 459 248 A1/U.S. 5,097,491, teach synchronous up/down gray counter); pertinent to increase/decrease of the time gray code.
Hughes et al., U.S. Patent No. 8,892,923, teach data Processing Apparatus and Method for Maintaining a Time Count Value in Normal and Power Saving Modes of Operation.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
All Internet e-mail communications will be made of record in the application file. PTO employees do not engage in Internet communications where there exists a possibility that sensitive information could be identified or exchanged unless the record includes a properly signed express waiver of the confidentiality requirements of 35 U.S.C. 122. This is more clearly set forth in the Interim Internet Usage Policy published in the Official Gazette of the Patent and Trademark on February 25, 1997 at 1195 OG 89.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see hop://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
