CTNF 19/177,659 CTNF 90978 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Application This office action is in response to the Application filed on 04/14/2025. Claims 1-20 are presented for examination. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/14/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has being considered by the examiner. Drawings The drawings submitted on 04/14/2025 are accepted. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Senior et al. (US2018/0329830 ; hereinafter Senior) in view of Pham et al. (US2017/0364446 ; hereinafter Pham) , and Benisty (US2024/0095165) . Regarding independent claims 1 and 11 , taking claim 1 as exemplary analysis, Senior teaches A method of operating a storage device including a memory device with a plurality of storage spaces respectively corresponding to a plurality of physical addresses (Senior in Fig. 1 & [0019]-[0020] discloses a processor-based system including a compressed memory system (102) with system memory having compressed data regions, each region including a plurality of memory blocks; memory access operations are performed on memory blocks identified by physical addresses) , the method comprising: a receiving operation of receiving at least one of K logical addresses for a write operation, where K is a natural number (Senior in Figs. 2-3 & [0030]-[0032] teaches that a compression circuit (216) receives a memory access request (218) comprising a virtual address (222) and write data (for write requests). A virtual address is a logical address in the system-memory context. The claim language “at least one of K logical addresses” is broad enough to cover receiving a single logical address ( K ≥ 1 ). Handling multiple outstanding memory requests (K requests in flight) is standard in processor and storage controllers and would be obvious) ; a determination operation of determining an N-bit value included in a location corresponding to a target physical address among the plurality of physical addresses, where N is a natural number (Senior in [0033] explicitly shows a full physical address (300) and an abbreviated physical address (302) where “N upper bits (306)” are omitted from the stored physical address; this necessarily involves determining that N-bit field at a defined bit location of the physical address) ; Senior teaches generating compressed physical addresses by removing N bits from physical addresses and maintaining corresponding mapping information. However, Senior does not explicitly teach searching among multiple logical-address mappings and selecting mappings that satisfy a predetermined relationship for inclusion in a compressed mapping entry. Pham in Fig. 3; [0038]-[0041] teaches replacing a “first sequence of … table entries comprising sequential physical addresses” with a compressed entry. To do this, the controller must examine multiple logical addresses and their corresponding physical addresses, deciding which groupings satisfy certain relations (e.g., sequential physical addresses) so they can be compressed together. This is a selection of logical addresses based on a deterministic relation to fields of the physical addresses. It would have been obvious to apply Pham's selection/grouping technique to Senior's abbreviated-address mapping scheme in order to increase compression efficiency and reduce mapping-table storage requirements. A person of ordinary skills in the art implementing Senior’s scheme for a batch of K outstanding memory requests would understand that the controller may search among pending logical addresses and select those whose modulus or other N-bit field relation matches a desired region index, so they can be grouped together for compression and allocation. This is a straightforward grouping optimization based on the same deterministic rule Senior uses to map virtual addresses to regions. Benisty is cited as a secondary reference because it teaches, in the specific context of SSD logical-to-physical (L2P) mapping tables, the field-based compression of physical addresses. In particular, Benisty in [0036]-[0038] discloses an L2P table implemented in host memory buffer or controller DRAM where each L2P entry stores only a fixed-width subset (e.g., 32 most significant bits) of a physical address and the remaining bits (least significant bits) are stored in a separate ECC/metadata structure, thereby explicitly illustrating storage of a “compressed physical address” in an SSD mapping table and placement of the removed N-bit field elsewhere. A person of ordinary skill in the art implementing the compressed mapping table architecture of Pham and the abbreviated physical address concept of Senior would have been motivated to adopt Benisty’s known MSB/LSB split within the compressed mapping entries to further reduce DRAM usage and metadata size in the same way as taught in Benisty, making the claimed removal of an N-bit field from the target physical address for use in compressed mapping information a predictable design choice. Thus, the combination of Senior, Pham and Benisty teaches a logical selection operation of searching for and selecting, from among the at least one of K logical addresses received in the receiving operation, a target logical address of a location including an N-bit value, obtained by applying a preset conversion rule to the N-bit value determined in the determination operation (Pham in Fig. 3; [0038]-[0041]. In Fig. 4 & [0034], Senior’s compression circuit selects one of 2 N compressed data regions (204(0)–204(2^N)) and corresponding free-list sets based on the modulus of the virtual address and 2 N . Thus, a deterministic function (modulus) of the logical/virtual address assigns it to a region whose N-bit index matches the remainder. Combined with the abbreviated physical address that omits N upper bits, the omitted bits are effectively encoded by the region index or other context determined from the logical address. The combination of Senior, Pham and Benisty further teaches and a first generation operation of generating, in response to the target logical address searched for in the logical selection operation, compressed mapping information by mapping, to the target logical address, a target compressed physical address generated by removing, from the target physical address, the N-bit value in the location corresponding to the target physical address (Senior in [0035] teaches metadata circuit (212) associates virtual addresses with abbreviated physical addresses that omit N upper bits of the full physical addresses. This is directly a mapping from logical address to compressed physical address generated by removing an N-bit field from the full physical address. Pham in [0028] shows compressed mapping entries in a mapping table that correlate logical addresses to storage locations in a compressed form. Accordingly, it would have been obvious to a person of ordinary skills in the art to implement compressed mapping information in which the physical-address component is stored in abbreviated form (Senior) within the compressed mapping table (Pham), mapping logical addresses to compressed physical addresses generated by removing the N-bit field) . 07-21-aia AIA Claim s 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Senior et al. (US2018/0329830 ; hereinafter Senior) in view of Pham (US2017/0364446 ; hereinafter Pham) , and Benisty (US2024/0095165) , further in view of Erez et al. (US2019/0065392; hereinafter Erez) . Regarding claim(s) 2 and 12 the combination of Senior, Pham and Benisty further teaches an operation of receiving target write data corresponding to the target logical address; and an operation of storing the target write data in a data sector of a target storage space corresponding to the target physical address ( Senior [0037], Pham [0077] and Benisty [0035] describe memory write operations where write data is received and written to a memory block selected based on the physical address derived from the mapping ). Senior , as discussed with respect to claim 1, teaches receiving logical addresses for write operations, determining N-bit information associated with physical addresses, generating compressed physical addresses by removing N bits from physical addresses, and generating compressed mapping information associating logical addresses with compressed physical addresses. Pham teaches examining multiple mapping entries, identifying groups of logical-to-physical mappings satisfying predetermined relationships, and generating compressed mapping entries for storage in compressed mapping structures. Pham further teaches storing compressed mapping information associated with logical-to-physical address translations. Benisty teaches compressed logical-to-physical mapping structures in which address information is reduced and represented in compressed form for reducing mapping-table overhead. However, Senior, Pham and Benisty do not explicitly disclose storing compressed logical-address-related information in a spare sector associated with the target storage space In analogous art of address translation, Erez in [0049]-[0050], Fig. 7. teaches storing LBA-related information in a spare area of a physical sector. Specifically, Erez explains that when multiple logical block addresses are represented within compressed data stored in a physical sector, information used to identify the respective LBAs is stored in a spare area of the physical sector. Such information may include offsets associated with different LBAs and that the information is stored in a spare area remaining in the physical sector after storage of compressed data. Erez further teaches that the spare-area information is used to distinguish compressed data corresponding to different logical block addresses stored within the compressed representation. See Erez [0049]-[0050]. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the compressed mapping system of Senior, as enhanced by Pham and Benisty, to store compressed logical-address-related information in a spare sector of the physical storage location as taught by Erez. Such modification would have provided a predictable advantage of reducing metadata overhead in primary mapping structures while maintaining information sufficient to identify logical-address relationships associated with compressed data stored in the corresponding physical location. Storing compressed logical-address information in a spare sector would further improve storage efficiency and facilitate reconstruction of logical-to-physical mappings while preserving available mapping-table capacity. Thus, the combination of Senior, Pham, Benisty and Erez teaches and storing a compressed logical address, in a spare sector of the target storage space. Regarding the limitation that the stored logical address is a compressed logical address obtained by removing an N-bit value from the logical address, Senior already teaches removing N-bit information from address representations to generate compressed address forms. Applying the same compression principle to logical-address metadata stored in the spare sector would have been an obvious design choice because compression of both sides of the mapping relationship (logical and physical address information) predictably reduces metadata storage requirements while preserving recoverability of the omitted information. Accordingly, it would have been obvious to store, in the spare sector of the target storage space, a compressed logical address obtained by removing the corresponding N-bit value from the logical address while storing the associated target write data in the data sector corresponding to the target physical address. Thus, the combination of Senior, Pham, Benisty and Erez teaches the compressed logical address being obtained by removing, from the target logical address, the N-bit value in the location corresponding to the target logical address. Allowable Subject Matter Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4-10 and 14-20 are objected to for depending on rejected/objected claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY C CHAN whose telephone number is (571)272-9992. The examiner can normally be reached on Monday - Friday 10 AM to 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached on (571)272-3642. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRACY C CHAN/Primary Examiner, Art Unit 2138 Application/Control Number: 19/177,659 Page 2 Art Unit: 2138 Application/Control Number: 19/177,659 Page 3 Art Unit: 2138 Application/Control Number: 19/177,659 Page 4 Art Unit: 2138 Application/Control Number: 19/177,659 Page 5 Art Unit: 2138 Application/Control Number: 19/177,659 Page 6 Art Unit: 2138 Application/Control Number: 19/177,659 Page 7 Art Unit: 2138 Application/Control Number: 19/177,659 Page 8 Art Unit: 2138 Application/Control Number: 19/177,659 Page 9 Art Unit: 2138 Application/Control Number: 19/177,659 Page 10 Art Unit: 2138 Application/Control Number: 19/177,659 Page 11 Art Unit: 2138
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