DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8, 12-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIGASHINO (US 20090179707 A1) in view Hashida et al (US 20140169442 A1).
As per claims 1 and 12, HIGASHINO teaches a digital clock and data recovery (CDR) system (see fig.3 and para [0005] for…. (an interpolated timing recovery (ITR) and para [0097] for… the configuration adopting the ITR method will be described with reference to FIG. 3), comprising: a sampling circuit that receives an input sampled signal (see fig.3 element 20 and para [0099] for….. the A/D converter 20 samples the RF signal on the basis of a clock signal having a fixed frequency output from an oscillator 27); and a data signal processing unit (see fig.3 element 5 and para [0082] for….. data signal processing unit 5 is configured so as to perform the digital sampling of the RF signal and para [0085] for….. uses an interpolator 28 to realize the so-called ITR method, as in the data signal processing unit 5 shown in FIG. 3 Examiner note: one of ordinary skill in the art would know that the claimed subject matter “digital monolithic circuit” is functionally equivalent to the data signal processing unit) that includes: a phase detector (PD) that determines a phase error (see fig.3 element 23 and para [0092] for…… The phase difference detector 23 calculates the phase difference between the current phase and a predetermined target phase (the appropriate sampling time) on the basis of the sampling value of the RF signal resulting from the PR equalization); and a fully digital clock (FDC) (see fig.3 element 29) that creates a digital clock used to recover digital data from the input sampled signal (see para [0085] for… in this configuration, an interpolation process is performed to the RF signal in accordance with the result of detection of a phase difference to achieve timing synchronization and para [0099] for…. an NCO 29 is provided to control the interpolation operation by the interpolator 28 and para [0103] for ……The interpolator 28 performs the interpolation to the RF signal supplied from the A/D converter 20 on the basis of the phase information calculated by the NCO 29. This interpolation allows the sampling value at the appropriate sampling time to be measured, thus achieving the same effect as in the case where the VCO 26 is used Examiner note: one of ordinary skill in the art would know that the claimed subject matter “recover digital data” is functionally equivalent to “achieve timing synchronization” or “allows the sampling value at the appropriate sampling time to be measured”)
However HIGASHINO does not explicitly teach a blind sampling circuit and a phase error which is used to determine a unit interval (UI) center.
HASHIDA teaches a blind sampling circuit (see fig.1 and para [0030] for… The blind-sampling CDR circuit includes a PLL circuit 11, an equalizer (EQ) 12, an analog/digital converter (ADC) 13, and a digital CDR processing circuit 14) and a phase error which is used to determine a unit interval (UI) center (see fig.1 elements 17 and 18 para [0015] for….. The DI 15 decides an interpolation coefficient for creating a value corresponding to the middle of 1 UI (unit interval) based on the phase information output from the filter 18 and par [0037] for….. the phase detector (PD) of the CDR method may utilize information at the middle of data and transition points of the data. As illustrated in FIG. 2, the data vary in the unit of unit interval (1 UI)).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO to include a blind sampling circuit and a phase error which is used to determine a unit interval (UI) center in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claims 2 and 13, HIGASHINO and HASHIDA in combination would teach an analog-to-digital converter (ADC) (see HIGASHINO fig.3 element 20); and an ADC sample clock(see HIGASHINO fig.3 element 27); wherein the ADC sample clock drives the ADC to provide the input sampled signal (see HIGASHINO para [0099] for…. in that the A/D converter 20 samples the RF signal on the basis of a clock signal having a fixed frequency output from an oscillator 27,) in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claims 3 and 14, HIGASHINO and HASHIDA in combination would teach wherein the FDC operates independently of the input sampled signal or the ADC sample clock (see HIGASHINO fig.3 element 29) in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claims 4 and 15, HIGASHINO and HASHIDA in combination would teach wherein the ADC samples an incoming analog signal without a feedback loop from the digital monolithic circuit (see HIGASHINO fig.3) in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claims 6 and 17, HIGASHINO and HASHIDA in combination would teach comprising a loop filter (LF) circuit (see HIGASHINO fig.3 element 24) that uses the phase error from the PD (see HIGASHINO fig.3 element 23) and provides a phase adjustment to the FDC (see HIGASHINO fig.3 element 29) in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claim 8, HIGASHINO and HASHIDA in combination would teach an interpolator that provides interpolated sample data (see fig.3 element 28) to the PD ) in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
-----Claim(s) 5, 10-11 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIGASHINO (US 20090179707 A1) in view Hashida et al (US 20140169442 A1) and in further view of Saed (US 8964925 B1).
As per claims 5 and 16, HIGASHINO and HASHIDA in combination do not explicitly teach wherein an ADC sample rate is greater than a baud rate.
Saed teaches wherein an ADC sample rate is greater than a baud rate(see col.1, lines 48-53 for…..To this end, the received signal is sampled at a rate higher than the baud rate. The over sampling rate may be 1.5.times., 2.times., 3.times. or even 4.times. depending on the desired interpolation and timing tracking performance at the given signal impairments).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO and Hashida to include wherein an ADC sample rate is greater than a baud rate in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claim 10, HIGASHINO and HASHIDA in combination do not explicitly wherein the CDR system resides in software.
Saed teaches wherein the CDR system resides in software (see col.16 ,lines 44-45 for…. the embodiments described herein are implemented as a software routine).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO and Hashida to include the CDR system resides in software in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claim 11, HIGASHINO and HASHIDA in combination do not explicitly wherein the CDR system is integrated in a custom ASIC.
Saed teaches wherein the CDR system is integrated in a custom ASIC (see col.3, lines 49-50 for…. At these increased rates, the most common implementation is an ASIC (Application Specific Integrated Circuit).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO and Hashida to include the CDR system is integrated in a custom ASIC in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
-----Claim(s) 7, 9, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIGASHINO (US 20090179707 A1) in view Hashida et al (US 20140169442 A1) and in further view of Aziz et al (US 9143367 B2).
As per claims 7 and 18, HIGASHINO and HASHIDA in combination do not explicitly teach at least one of a feed-forward equalizer (FFE) and a decision feedback equalizer (DFE), wherein the at least one of the FFE and DFE provide equalized sampled data to the PD.
Aziz et al teaches at least one of a feed-forward equalizer (FFE) (see fig.2 element 210 and col.3, line 48 for…. a feed-forward equalizer (FFE) 210) and a decision feedback equalizer (DFE) (see fig.2 element 212 and col.3, line 49 for…. a digital decision-feedback equalizer (DIGDFE) 212) , wherein the at least one of the FFE (210) and DFE (212) provide equalized sampled data to the PD (see fig.2 element 216 and col.4, lines 60-62 for… MUX 222, in response to control signal PDSEL, selects one set of phase detector inputs out of three sets of outputs from ADC 208, FFE 210, and DIGDFE 212 and forwards the one set of the phase detector inputs to PD1 216).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO and Hashida to include wherein the at least one of the FFE and DFE provide equalized sampled data to the PD in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
As per claims 9 and 19, HIGASHINO and HASHIDA in combination do not explicitly teach wherein a feed-forward equalizer is placed ahead of the interpolator and operates on the sampled signal, rather than interpolated samples.
Aziz et al teaches wherein a feed-forward equalizer ((see fig.2 element 210 and col.3, line 48 for…. a feed-forward equalizer (FFE) 210)) is placed ahead of the interpolator (see fig.2 element 214 and col.3, lines 49-50 for… a digital interpolation filter (DIF) bank 214,) and operates on the sampled signal, rather than interpolated samples.
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify HIGASHINO and Hashida to include wherein a feed-forward equalizer (FFE) is placed ahead of the interpolator and operates on the sampled signal, rather than interpolated samples in order to reduce the operation speed of sampling phase data interpolation recovery circuit. Furthermore the interpolator would perform a process for interpolating data output from the ADC using an interpolation coefficient for indicating interpolation values obtained between two adjacent sample values. Such modification would enhance the data clock recovery circuit to achieve the optimum synchronization between input data sampler and sampling clock.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130315346 A1 or US 20130181757 A1 or US 20140112424 A1 US 20070172002 A1 US.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMMANUEL BAYARD whose telephone number is (571)272-3016. The examiner can normally be reached 6-9.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahn K Sam can be reached at 571-272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMMANUEL BAYARD/Primary Examiner, Art Unit 2633
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