DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant’s claim for the benefit of prior-filed applications 17/683,980, now issued as US 11,940,912, and 18/442,248, now issued as US 12,314,177 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 112(a) as follows:
As identified in the rejections concerning 35 U.S.C. 112(a), the instant application’s specification does not provide sufficient disclosure to demonstrate possession of the claimed feature, namely where “for each section of a plurality of sections of an address mapping table, determining whether a number of updates to the address mapping table satisfies a threshold criterion”. Upon review of parent applications 17/683,980 and 18/442,248, the parent applications similarly fail to disclose the claimed feature identified, and as such the claims do not receive the benefit of priority in this action. All claims are examined in this action with an effective filing date of April 14, 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 9, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature in the independent claims where the determination is made for each section of the plurality of the sections must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8, and 15 recite, using claim 1 for example language,
For each section of a plurality of sections of an address mapping table, determining whether a number of updates to the address mapping table satisfies a threshold criterion.
The confusion relates to the phrase “for each section of a plurality of sections”, as the phrase within the claim language does not clarify whether one determination is sufficient for each section, or whether the determination must be performed individually for each section, leading to an indefinite claim scope, as it is not clear how many times the determining must be performed. In the context of the specification, “for each section” is understood to represent an individual action/data structure that is maintained for a single section, see for example [0017] where “the memory sub-system controller can further keep track of a respective dirty count for each section of the L2P table”, suggesting an individual dirty count, and see also [0036,0037], see also [0040,0041] where an action is performed for each section, with resetting an individual counter for each section, see also [0043], where identifying a section with a highest section dirty count requires comparing the section dirty count for each section at an individual, per section basis. Thus, it is understood that the specification utilizes “for each section” to refer to an individual data structure or action associated with an individual section matching the latter interpretation, with no evidence that “for each section” refers to the sufficiency of the action as in the former interpretation. For the purpose of examination, while no language suggestion is provided here, it is assumed that the phrase “for each section” requires that the “determining whether a number of updates to the address mapping table satisfies a threshold criterion” is performed individually for each section, i.e. multiple times, one for each section.
The dependent claims are rejected for dependence on one of the independent claims as identified above.
Claims 2, 9, and 16 recite, using claim 2 for example language, wherein the number of updates to the address mapping table comprises:
Maintaining a number of updates to each section…
Combining the number of updates to each section…
The issue with this language is that from the independent claims, “the number of updates to the address mapping table” is understood to be a noun representing the number. The dependent claims then add that the noun comprises a number of method steps, which renders the claims indefinite, as it is no longer clear what “the number of updates to the address mapping table” is supposed to be. For the purpose of examination, while no language suggestion is provided, the maintaining and combining limitations are interpreted to be required, but separate from “the number of updates to the address mapping table”. For the purpose of claims 2 and 16, these are additional operations that are executed by their respective processing devices, and for the purpose of claim 9, these are additional method steps.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
MPEP § 2163(I) provides that “”it is now well accepted that a satisfactory description may be found in originally-filed claims or any other portion of the originally-filed specification. See In re Koller, 613 F.2d 819, 204 USPQ 702 (CCPA 1980); In re Gardner, 475 F.2d 1389, 177 USPQ 396 (CCPA 1973); In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). However, that does not mean that all originally-filed claims have adequate written support. The specification must still be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings.”
As discussed in the section immediately preceding regarding the interpretation of the independent claims, based on the usage of the phrase “for each section” in the specification, it is assumed that the limitation “for each section of a plurality of sections of an address mapping table, determining whether a number of updates to the address mapping table satisfies a threshold criterion” requires performing the “determining” limitation multiple times, one for each section.
However, in a review of the specification, this determining limitation is not performed multiple times, one for each section. Whenever the specification refers to determining whether a total dirty count of the L2P table (understood to match with the number of updates to the address mapping table) satisfies a threshold, this action is only understood to be performed once overall, instead of multiple times, see [0017, 0036, 0042, 0044, 0049, 0050]. Notably, in [0050] the specification specifies that a total dirty count satisfies the threshold criterion, and in response to that, then the dirty count for each section is compared, showing that the specification distinguishes whether an action is performed for each section or not. This leads to a determination that the specification fails to convey possession of the claimed invention, meriting a rejection under 35 U.S.C. 112(a).
Examiner notes that removing the phrase “for each section of a plurality of sections of an address mapping table” would sufficiently overcome this rejection, as the specification clearly has support for an overall determination that the number of updates to the address mapping table satisfy a threshold criterion.
The dependent claims are rejected due to dependence on one of the independent claims.
Application Status
For the purpose of compact examination, examiner acknowledges that the following rejections under 35 U.S.C. 103 and double patenting do not apply to the claims as currently discussed and interpreted above. However, as the suggestion for amendment to address the rejection under 35 U.S.C. 112(a) is relatively straightforward (i.e. removing the “for each section of a plurality of sections” language), the following rejections will help expedite prosecution of the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld et al. (US 2022/0043746, as presented in applicant’s IDS) in view of Zeng et al. (US 2020/0272577).
Regarding claim 1, Winterfeld teaches a system (Fig. 1, system 100) comprising:
a non-volatile memory device (Fig. 1, memory devices 130, described as non-volatile in [0020]); and
a processing device, operatively coupled with the non-volatile memory device, to perform operations (Fig. 1, controller 115 containing processor 117, where the processor can execute instructions stored in local memory to control operations of the memory subsystem 110, see [0031]) comprising:
determining whether a number of updates to an address mapping table satisfies a threshold criterion (“determining, at operation 540, that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value,” [0072], where the write count is understood to be a number of data page writes, see [0019], reading upon a number of updates, as any writes also reflects a number of updates to the mapping table, see [0016]);
writing a section of the address mapping table to the non-volatile memory device (“Responsive to determining, at operation 540, that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, the processing device, at operation 550, copies the region of the L2P table to a non-volatile memory, as described in more detail herein above,” [0072]; see also [0038] and Fig. 2 where identifiable regions of the L2P table are cached in the volatile memory).
Winterfeld fails to teach the operations comprising:
identifying a section among the plurality of sections with a highest number of updates to the section.
As a result, Winterfeld also fails to teach where the section written to the non-volatile memory device is specifically the one identified with a highest number of updates.
Zeng’s disclosure is related to cache management of translation metadata and as such comprises analogous art in the same field of endeavor of mapping information management.
As part of this disclosure, Zeng generally discloses where FTL pages/blocks can be cached as metadata in a cache, see [0043], where a dirty map can include information on whether a FTL page is dirty or not, see [0095], and specifically, that “in some aspects, the dirty map 460 may be configured to track a number of dirty entries 252 of respective FTL pages 254; the dirty map 460 may comprise dirty counts for respective FTL pages 254, each indicating a number of entries 252 to be flushed to the FTL page 254,” [0095]. Further, “The cache manager 160 may be configured to implement background flush and/or write-back operations based on, inter alia, the dirty map 460. The cache manager 160 may be configured to identify dirty FTL pages 254 based on the dirty map 460 (based on dirty indicators and/or dirty counts of respective FTL pages 254 maintained in the 460) and implement (or schedule) operations to update the dirty FTL pages 254 in one or more background flush operations. The cache manager 160 may be configured to select FTL pages 254 for update operations based on any suitable criteria, such as dirty counts of the FTL pages 254 (FTL pages 254 with higher dirty counts may be selected before FTL pages 254 having lower dirty counts,” [0096].
An obvious modification can be identified: incorporating Zeng’s ability to track dirty counts for individual sections of cached metadata, not just the overall write count as provided in Winterfeld, and further identifying pages for flushing based on the dirty count, with Zeng specifically providing that a FTL page with a higher dirty count may be selected before FTL with lower dirty counts. Such a modification reads upon the identification limitation, as well as where the region flushed back to non-volatile memory is the one with the highest update count.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Zeng’s disclosure/use of dirty counts for individual FTL pages and selection for flushing based on this dirty count into Winterfeld’s system, as this ensures that the system can identify the best region to flush based on updating/persisting the greatest number of dirty entries.
Regarding claim 2, the combination of Winterfeld and Zeng teaches the system of claim 1, wherein the number of updates to the address mapping table comprises:
maintaining a number of updates to each section of the plurality of sections (as discussed in the claim 1 rationale, Zeng [0095] provides for individual dirty entry counts for cached FTL pages); and
combining the number of updates to each section of the plurality of sections (as discussed in the claim 1 rationale, Winterfeld provides for an overall write count in [0016,0019]; necessarily, an overall write count will be based on a combination of dirty entry counts for individual regions).
Regarding claim 3, the combination of Winterfeld and Zeng teaches the system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, decrementing, for the section, the number of updates to the address mapping table by the number of updates to the section (as an extension to the flushing process disclosed in claim 1, Zeng [0098] provides that “The cache manager 160 may be further configured to clear the dirty flag of the selected FTL page 254 in the dirty map 460 in response to completing the flush operation (e.g., in response to storing the updated FTL page 254 on the NVM medium 424). Clearing the dirty flag of an FTL page 254 may comprise setting the dirty flag to indicate that the FTL page 254 is clean (e.g., not dirty and/or has a dirty count of 0);” as Winterfeld [0016,0019] provides tracking an overall dirty count, then necessarily, when a FTL page is reset to clean, then the overall dirty write count is reduced by that number).
Regarding claim 4, the combination of Winterfeld and Zeng teaches the system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, setting the number of updates to the section to an initial value (as an extension to the flushing process disclosed in claim 1, Zeng [0098] provides that “The cache manager 160 may be further configured to clear the dirty flag of the selected FTL page 254 in the dirty map 460 in response to completing the flush operation (e.g., in response to storing the updated FTL page 254 on the NVM medium 424). Clearing the dirty flag of an FTL page 254 may comprise setting the dirty flag to indicate that the FTL page 254 is clean (e.g., not dirty and/or has a dirty count of 0)”).
Regarding claim 5, the combination of Winterfeld and Zeng teaches the system of claim 1, wherein identifying the section of the plurality of sections based on the number of updates to the section comprises:
comparing the number of updates to the section for each section (as cited in the claim 1 rationale, Zeng [0095,0096] provides for the ability to track a number of dirty counts for each FTL page, and the selection of the page to flush is based on a comparison to locate a FTL page with a higher number of dirty entries); and
identifying a section with a highest number of updates to the section (as cited in the claim 1 rationale, Zeng [0095,0096] provides for the ability to track a number of dirty counts for each FTL page, and the selection of the page to flush is based on a comparison to locate a FTL page with a higher number of dirty entries).
Regarding claim 6, the combination of Winterfeld and Zeng teaches the system of claim 1, wherein writing the section of the address mapping table to the non- volatile memory device comprises:
writing a plurality of dirty entries of the section of the address mapping table to the non- volatile memory device (Winterfeld Fig. 2 depicts a cached L2P region that is dumped to the non-volatile memory device containing multiple entries; Zeng [0095,0096] identifies multiple dirty entries in a FTL page count to be flushed).
Claim 8 is a method claim reciting limitations identical to the operations performed by the processing device in claim 1 and therefore can be rejected according to the same rationale of claim 1.
Claims 9-13 are rejected according to the same rationale of claims 2-6 respectively.
Regarding claim 15, Winterfeld teaches a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (“The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110,” [0031], see also [0083,0085]) identical to the operations of claim 1 and therefore rejected according to the same rationale.
Claims 16-20 are rejected according to the same rationale of claims 2-6 respectively.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld in view of Zeng and further in view of Booth et al. (US 2017/0322888).
Regarding claim 7, the combination of Winterfeld and Zeng teaches the system of claim 1, but fails to teach wherein the threshold criterion is set to keep a number of journal entry replays below a threshold number of journal entry replays during a reconstruction of the address mapping table after a power loss event.
While Winterfeld discusses the context of an asynchronous power loss event as a motivation for repeatedly saving snapshots of the L2P table, see [0015,0016], and also discloses replaying journaled updates after an APL event, see [0016], Winterfeld does not explicitly cite that the write count or threshold count is set based on a number of journal replays.
Booth’s disclosure is related to a log table that manages logical to physical address translation tables, and as such comprises analogous art in the same field of endeavor of mapping table management.
As part of this disclosure, Booth provides for a log list to track L2P mappings since a previous dump, see [0040,0041]. Specifically, Booth provides that “Controller 8 may constrain the length of the log list to remain at within a maximum or threshold length. The maximum length may reflect a length that controller 8 can replay or “journal” within the backup time (or “power cap”) provided by power supply 11 at power loss. For instance, controller 8 may limit the maximum log list length such that the power cap provided by power supply 11 is sufficiently long (in units of time) for controller 8 to write the log list into non-volatile memory array 10. Upon a subsequent power-up, controller 8 may update the last L2P table committed to NVMA 10 using the log list. The process of iterating through the log list to update the L2P table may be referred to as “replaying,” “walking through,” “stepping through,” or “journaling” the log list. Controller 8 replays the log list in the same order in which the log list was recorded, in serial fashion,” [0042].
An obvious modification can be identified: incorporating Booth’s disclosure of constraining the length of a list based on the length that the controller can replay upon powering up into Winterfeld’s disclosure. Such a modification reads upon the limitation of the claim, as Booth’s disclosure explicitly ties the length of a list associated with cached items to be committed to non-volatile memory with the functionality of journal replaying after a power loss event.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Booth’s disclosure of tying a threshold length/size to a controller’s replay ability into Winterfeld’s disclosure, as this ensures that a controller isn’t burdened beyond capacity with committing or replaying too many updates to an L2P update table upon power recovery.
Claim 14 is rejected according to the same rationale of claim 7.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 of U.S. Patent 11,940,912 and claims 1-20 of U.S. Patent 12,314,177 contain every element of claims 1-20 of the instant application, as can be shown in the following tables, and as such anticipates claims 1-20 of the instant application. “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).” ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
For clarity of record, only claims 1-7 of the instant application is shown in the tables, as claims 8-20 only differ in statutory category.
Claim 1, instant application
Claim 1, US 11,940,912
A system comprising:
a non-volatile memory device; and
a processing device, operatively coupled with the non-volatile memory device, to perform operations comprising:
determining whether a number of updates to the address mapping table satisfies a threshold criterion;
identifying a section among the plurality of sections with a highest number of updates to the section; and
writing the section of the address mapping table to the non-volatile memory device.
A system comprising:
a non-volatile memory device; and
a processing device, operatively coupled with the volatile and non-volatile memory devices, to perform operations comprising:
…
determining that the total dirty count for the L2P table satisfies a threshold criterion;
in response to determining that the total dirty count for the L2P table satisfies the threshold criterion, identifying, based on the respective section dirty counts, a first section of the plurality of sections with a highest section dirty count; and
writing the first section of the L2P table to the non-volatile memory device.
Claim 2, instant application
Claim 1, US 11,940,912
The system of claim 1, wherein the number of updates to the address mapping table comprises:
maintaining a number of updates to each section of the plurality of sections; and
combining the number of updates to each section of the plurality of sections.
…
maintaining a logical-to-physical (L2P) table, wherein a plurality of sections of the L2P table is cached in the volatile memory device;
maintaining a total dirty count for the L2P table, wherein the total dirty count comprises a total number of updates to the L2P table;
maintaining, for the plurality of sections, respective section dirty counts, wherein each respective section dirty count comprises a total number of updates to a corresponding section;
Claim 3, instant application
Claim 2, US 11,940,912
The system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, decrementing, for the section, the number of updates to the address mapping table by the number of updates to the section.
The system of claim 1, further comprising:
in response to writing the first section of the L2P table to the non-volatile memory device, decrementing the total dirty count by the section dirty count for the first section.
Claim 4, instant application
Claim 3, US 11,940,912
The system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, setting the number of updates to the section to an initial value.
The system of claim 1, further comprising:
in response to writing the first section of the L2P table to the non-volatile memory device, setting the section dirty count for the first section to an initial value.
Claim 5, instant application
Claim 5, US 11,940,912
The system of claim 1, wherein identifying the section of the plurality of sections based on the number of updates to the section comprises:
comparing the number of updates to the section for each section; and
identifying a section with a highest number of updates to the section.
The system of claim 1, wherein identifying, based on the respective section dirty counts, the first section of the plurality of sections with the highest section dirty count comprises:
comparing the section dirty count for each section.
Claim 6, instant application
Claim 6, US 11,940,912
The system of claim 1, wherein writing the section of the address mapping table to the non- volatile memory device comprises:
writing a plurality of dirty entries of the section of the address mapping table to the non- volatile memory device.
The system of claim 1, wherein writing the first section of the L2P table to the non-volatile memory device comprises:
writing a plurality of dirty entries of the first section of the L2P table to the non-volatile memory device.
Claim 7, instant application
Claim 7, US 11,940,912
The system of claim 1, wherein the threshold criterion is set to keep a number of journal entry replays below a threshold number of journal entry replays during a reconstruction of the address mapping table after a power loss event.
The system of claim 1, wherein the threshold criterion is set to keep a number of journal entry replays below a threshold number of journal entry replays during a reconstruction of the L2P table after a power loss event.
The following table shows the comparison with the claims of US 12,314,177.
Claim 1, instant application
Claim 1, US 12,314,177
A system comprising:
a non-volatile memory device; and
a processing device, operatively coupled with the non-volatile memory device, to perform operations comprising:
determining whether a number of updates to the address mapping table satisfies a threshold criterion;
identifying a section among the plurality of sections with a highest number of updates to the section; and
writing the section of the address mapping table to the non-volatile memory device.
A system comprising:
a non-volatile memory device; and
a processing device, operatively coupled with the non-volatile memory device, to perform operations comprising:
…
determining that the total count for the address mapping table satisfies a threshold criterion;
identifying, based on the respective section counts, a first section of the plurality of sections with a highest section count; and
writing the first section of the address mapping table to the non-volatile memory device.
Claim 2, instant application
Claim 1, US 12,314,177
The system of claim 1, wherein the number of updates to the address mapping table comprises:
maintaining a number of updates to each section of the plurality of sections; and
combining the number of updates to each section of the plurality of sections.
…
maintaining a total count for an address mapping table, wherein the total count comprises a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections;
maintaining, for the plurality of sections, respective section counts, wherein each respective section count comprises a total number of updates to a corresponding section;
Claim 3, instant application
Claim 2, US 12,314,177
The system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, decrementing, for the section, the number of updates to the address mapping table by the number of updates to the section.
The system of claim 1, further comprising:
in response to writing the first section of the address mapping table to the non-volatile memory device, decrementing the total count by the section count for the first section.
Claim 4, instant application
Claim 3, US 12,314,177
The system of claim 1, wherein the processing device is to perform operations further comprising:
in response to writing the section of the address mapping table to the non-volatile memory device, setting the number of updates to the section to an initial value.
The system of claim 1, further comprising:
in response to writing the first section of the address mapping table to the non-volatile memory device, setting the section count for the first section to an initial value.
Claim 5, instant application
Claim 5, US 12,314,177
The system of claim 1, wherein identifying the section of the plurality of sections based on the number of updates to the section comprises:
comparing the number of updates to the section for each section; and
identifying a section with a highest number of updates to the section.
The system of claim 1, wherein identifying the first section of the plurality of sections based on the respective section counts comprises:
comparing the section count for each section; and
identifying a section with a highest section count.
Claim 6, instant application
Claim 6, US 12,314,177
The system of claim 1, wherein writing the section of the address mapping table to the non- volatile memory device comprises:
writing a plurality of dirty entries of the section of the address mapping table to the non- volatile memory device.
The system of claim 1, wherein writing the first section of the address mapping table to the non-volatile memory device comprises:
writing a plurality of dirty entries of the first section of the address mapping table to the non-volatile memory device.
Claim 7, instant application
Claim 7, US 12,314,177
The system of claim 1, wherein the threshold criterion is set to keep a number of journal entry replays below a threshold number of journal entry replays during a reconstruction of the address mapping table after a power loss event.
The system of claim 1, wherein the threshold criterion is set to keep a number of journal entry replays below a threshold number of journal entry replays during a reconstruction of the address mapping table after a power loss event.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Volpe (US 10,733,110) discloses managing eviction of memory and mapping table entries based on write counts,
Nellans et al. (US 2013/0080732) discloses loading/persisting mapping entries from/to non-volatile memory,
Kotte et al. (US 2016/0342509) discloses managing mapping information with associated counters for each region,
Noé (US 2017/0060433) discloses flushing memory into lower non-volatile memory and maintaining a block count,
Zhang et al. (US 2017/0242584, as provided in applicant’s IDS) discloses managing mapping table information in volatile and non-volatile memory,
Jenne et al. (US 2018/0032439) discloses tracking a count of dirty cache lines, and resetting it to zero upon flushing the cache lines to persistent memory,
Yen et al. (US 2020/0151108) discloses tracking updated counts for LBA’s in a mapping table, with the ability to flush the mapping table for updates,
Bono et al. (US 2020/0250087) decrements dirty counts based on the number of flushed data structures,
Byun (US 2020/0364157) discloses loading/evicting mapping data in a memory system,
Navon et al. (US 2020/0409856) discloses loading and evicting address table information,
Lee et al. (US 2020/0409845) discloses managing and flushing address mapping table information,
Harris et al. (US 11,714,748), Yu et al. (US 2022/0100608), Guan et al. (US 2023/0065617) and Harris et al. (US 2023/0289285) disclose managing address mapping table in a power loss recovery situation; examiner acknowledges that these disclosures would not qualify as prior art if the priority issue is corrected and the claims are examined with an effective filing date of March 1, 2022.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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