Prosecution Insights
Last updated: August 17, 2026
Application No. 19/177,996

Memory-Request Priority Up-Leveling

Non-Final OA §DP
Filed
Apr 14, 2025
Priority
Nov 05, 2020 — nonprovisional of PCTUS2020059061 +1 more
Examiner
MAMO, ELIAS
Art Unit
Tech Center
Assignee
Google LLC
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
774 granted / 934 resolved
+22.9% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
10 currently pending
Career history
946
Total Applications
across all art units

Statute-Specific Performance

§101
7.1%
-32.9% vs TC avg
§103
60.3%
+20.3% vs TC avg
§102
12.1%
-27.9% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 934 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-8, 11 and 14-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 and 11-18 of U.S. Patent No. 12,277,075. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar with minor differences and not distinguishing the overall appearance of one over the other. NOTE: the claims of instant application are anticipated by the claims of the patent, as outlined in the table below. Current application 19/177,996 US Patent 12,277,075 1. A method for memory-request priority adjustment performed by a memory controller, the method comprising: receiving a memory request from a client over a virtual channel, the memory request having an original; priority level; adding the memory request to a memory request buffer along with: an indication of a virtual channel identification (VCID) of the virtual channel; and the original for priority level of the memory request; determining that an adjustment indication corresponding to the VCID is asserted; increasing or decreasing the original priority level of the memory request to an adjusted priority level based on the adjustment indication that is asserted; determining that one or more other memory requests within the memory request buffer have an indication of the VCID; and increasing or decreasing respective original priority levels of the one or more other memory requests to respective adjusted priority levels based on the adjustment indication that is asserted. 1. A method for memory request priority adjustment performed by a memory controller, the method comprising: receiving a memory request from a client over a virtual channel, VC, the memory request having an original priority-level; adding the memory request to a memory request buffer along with: an indication of a virtual channel identification, VCID, of the VC; and the original priority-level for the memory request; … determining that an adjustment indication corresponding to the VCID is asserted; and increasing or decreasing the original priority-level of the memory request to an adjusted priority level based on the asserted adjustment indication. 11. The method of claim 1, further comprising: determining that one or more other memory requests within the memory request buffer have an indication of the VCID; and increasing or decreasing, based on the adjustment indication, respective original priority-levels of the other memory requests to respective adjusted priority levels. 2. The method of claim 1, wherein the adjustment indication is asserted via a side channel to the memory controller. 2. The method of claim 1, wherein the adjustment indication is asserted via a side channel to the memory controller. 3. The method of claim 1, wherein the adjustment indication is asserted from the client or another client using the virtual channel. 3. The method of claim 1, wherein the adjustment indication is asserted from the client or another client using the VC. 4. The method of claim 1, further comprising determining an adjustment amount comprising: an amount by which to increase or decrease the original priority level; or a value for the adjusted priority level. 4. The method of claim 1, further comprising determining an adjustment amount comprising: an amount by which to increase or decrease the original priority-level; or a value for the adjusted priority level. 5. The method of claim 1, further comprising: determining that the adjustment indication is no longer asserted; and responsive to determining that the adjustment indication is no longer asserted, returning the adjusted priority level of the memory request to the original priority level. 5. The method of claim 1, further comprising: determining that the adjustment indication is no longer asserted; and responsive to the determining that the adjustment indication is no longer asserted, returning the adjusted priority level of the memory request to the original priority-level. 6. The method of claim 1, further comprising granting the memory request based on the adjusted priority level. 6. The method of claim 1, further comprising granting the memory request based on the adjusted priority level. 7. The method of claim 1, wherein the original priority level is assigned by the client from which the memory request is received. 7. The method of claim 1, wherein the original priority-level is assigned by the client. 8. The method of claim 1, wherein the virtual channel is based on the client or associated with the client. 8. The method of claim 1, wherein the VC is based on the client. 11. The method of claim 10, wherein the second memory request was received over a second virtual channel that different than the first virtual channel. 9. The method of claim 1, wherein the other memory requests were received over one or more VCs that are different than the VC. 14. A memory controller comprising: an interface configured to operably couple the memory controller to a client via a virtual channel; the memory controller configured to receive a memory request from the client over the virtual channel, the memory request having an original priority level; a memory request buffer; and a memory request priority level adjustment module configured to: add the memory request to the memory request buffer along with: an indication of a virtual channel identification (VCID) of the virtual channel; and the original priority level of the memory request; determine that an adjustment indication corresponding to the VCID is asserted; increase or decrease the original priority level of the memory request to an adjusted priority level based on the adjustment indication that is asserted; determine that one or more other memory requests within the memory request buffer have an indication of the VCID; and increase or decrease respective original priority levels of the one or more other memory requests to respective adjusted priority levels based on the adjustment indication that is asserted. 12. A memory controller comprising: an interface configured to operably couple the memory controller to a client via a virtual channel (VC); a memory request buffer; and a memory request priority-level adjustment module configured to: receive a memory request from the client over the VC, the memory request having an original priority-level; add the memory request to the memory request buffer along with: an indication of a virtual channel identification, VCID, of the VC; and the original priority-level for the memory request; determine if another memory request in the memory request buffer is related to the memory request by comparing a transaction identification of the memory request to respective transaction identifications for other memory requests within the memory request buffer or comparing one or more memory addresses of the memory request to respective memory addresses for other memory requests within the memory request buffer; determine that an adjustment indication corresponding to the VCID is asserted; and increase or decrease the original priority-level of the memory request to an adjusted priority level based on the asserted adjustment indication. 15. The memory controller of claim 14, wherein the adjustment indication is asserted via a side channel to the memory controller. 13. The memory controller of claim 12, wherein the adjustment indication is asserted via a side channel to the memory controller. 16. The memory controller of claim 14, wherein the adjustment indication is asserted from the client or another client using the virtual channel. 14. The memory controller of claim 12, wherein the adjustment indication is asserted from the client or another client using the VC. 17. The memory controller of claim 14, wherein the memory request priority level adjustment module is further configured to determine an adjustment amount for the memory request based on: an amount by which to increase or decrease the original priority level; or a value for the adjusted priority level. 15. The memory controller of claim 12, wherein the memory request priority-level adjustment module is further configured to determine an adjustment amount for the memory request based on: an amount by which to increase or decrease the original priority-level; or a value for the adjusted priority level. 18. The memory controller of claim 14, wherein the memory request priority level adjustment module is further configured to: determine that the adjustment indication is no longer asserted; and responsive to the determination that the adjustment indication is no longer asserted, return the adjusted priority level of the memory request to the original priority level. 16. The memory controller of claim 12, wherein the memory request priority-level adjustment module is further configured to: determine that the adjustment indication is no longer asserted; and responsive to the determination that the adjustment indication is no longer asserted, return the adjusted priority level of the memory request to the original priority-level. 19. The memory controller of claim 14, wherein the memory controller is configured to grant the memory request based on the adjusted priority level. 17. The memory controller of claim 12, wherein the memory controller is configured to grant the memory request based on the adjusted priority level. 20. The memory controller of claim 14, wherein: the original priority level is assigned by the client; or the virtual channel is based on the client or associated with the client. 18. The memory controller of claim 12, wherein: the original priority-level is assigned by the client; or the VC is based on the client. Allowable Subject Matter Claims 1-20 are objected to because of the presence of the obviousness type double patenting (see above) but would be allowable if the rejection is overcome. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chung et al. (US 8,505,016), Cohen et al. (US 4,807,111), Eckert (US 9,195,618), Masuda et al. (US 7,130,903), Nguyen et al. (US 5,712,851), Quinquis et al. (5,638,377) and Wang (US 8,539,129) do teach method and system for memory request scheduling with priority control. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HENRY TSAI can be reached at 571-272-4176. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Elias Mamo/Primary Examiner, Art Unit 2184
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Prosecution Timeline

Apr 14, 2025
Application Filed
Jul 22, 2025
Response after Non-Final Action
Jul 14, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+5.8%)
2y 6m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 934 resolved cases by this examiner. Grant probability derived from career allowance rate.

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