DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/14/2025 is in compliance with the provisions on 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the channel" in line 7. There is insufficient antecedent basis for this limitation in the claim. Alternatively, it is unclear if “the channel” is referring to “a charge transfer channel” of line 4.
Claims 2-16 are rejected as being dependent on claim 1.
Claims 2 and 4-16 recite “The device according to…”. There is insufficient antecedent basis for this limitation in the claim. Alternatively, it is unclear if “The device” is referring to “An electronic device” of line 1.
Claim 17 recites the limitation "the channel" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. Alternatively, it is unclear if “the channel” is referring to “a charge transfer channel” of line 2.
Claim 17 recites the limitation "the electrostatic potentials of the first semiconductor region and the second semiconductor region" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
Claims 18-19 are rejected as being dependent on claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, 10-11, 13-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ma et al. (US 2024/0236525 A1).
Regarding claim 1, Ma et al. (hereafter referred as Ma) teaches an electronic device (Ma, Figs. 1-2, Paragraph 0031, “image sensor”), comprising:
a pixel (Ma, Figs. 1-2, pixel 100, Paragraph 0031) including:
a photodiode (Ma, Fig. 1-2, PD 102) located in a substrate (Ma, Figs. 1-2, substrate 130, Paragraphs 0031-0032);
a charge transfer channel (Ma, Figs. 1-2, P1 106, P2 108 and P3 110, Paragraphs 0032-0033) comprising a first semiconductor region (Ma, Figs. 1-2, P1 106) and a second semiconductor region (Ma, Figs. 1-2, P2 108), the second semiconductor region being separated from the photodiode by the first semiconductor region (Ma, Figs. 1-2, P2 108 is separated from PD 102 by P1 106.); and
a trench surrounding the channel (Ma, Figs. 1-2, dielectric material 150, G1 112, G2 114 and G3 116, Paragraphs 0033-0034), the trench comprising a first conductive core (Ma, Figs. 1-2, G1 112), a second conductive core (Ma, Figs. 1-2, G2 114) and an insulating sheath (Ma, Figs. 1-2, dielectric material 150) which separates the first and second conductive cores from the first and second semiconductor regions, the first conductive core laterally surrounding the first semiconductor region and the second conductive core laterally surrounding at least partially the second semiconductor region (Ma, Figs. 1-2, Paragraph 0034, “G1 112, G2 114, and G3 116 may each have a ring-shape geometry, thus completely enclosing their corresponding modulation regions P1 106, P2 108, and P3 110”).
Regarding claim 2, Ma teaches the device according to claim 1 (see claim 1 analysis), further comprising control circuit (Ma, Fig. 5, row logic and drivers circuit(s) 552, Paragraph 0041) for generating control voltages for biasing the first conductive core and the second conductive core (Ma, Figs. 4-5, Paragraphs 0038-0040).
Regarding claim 3, Ma teaches the electronic device according to claim 2 (see claim 2 analysis), wherein the control circuit is configured to:
bias the first conductive core and the second conductive core during a pixel integration operation so that electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are at a high value (Ma, Figs. 4A and 4B, Exposure period 432, Paragraph 0038, The electrostatic potentials (potential profile relative to PD 402) of P1 and P2 are high.);
bias the first conductive core and the second conductive core during a pixel charge transfer operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are, respectively, at a first low value and at a second low value, the first low value being higher than the second low value (Ma, Figs. 4A and 4C, Paragraph 0039);
bias the first conductive core and the second conductive core during a first step of passage from the pixel charge transfer operation to a pixel readout operation so that the electrostatic potential of the first semiconductor region is at the high value and the electrostatic potential of the second semiconductor region is at the second low value (Ma, Figs. 4A and 4D, Paragraph 0040); and
bias the first conductive core and the second conductive core during a second step of passage from the pixel charge transfer operation to the pixel readout operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are equal to the high value (Ma, Fig. 4A, End of period 436 where control signals G1-G3 are low., Examiner notes: A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. (see MPEP 2114.II)).
Claim 17 us rejected for the same reasons as claim 3.
Regarding claim 4, Ma teaches the device according to claim 3 (see claim 3 analysis), wherein control voltages applied to the first conductive core and the second conductive core by the control circuit for biasing are different at least during a pixel operation (Ma, Fig. 4A, Paragraph 0039, Control signal to G1 and control signal to G2 are different control voltages. Further, “voltages of different values may be applied to G1 412 and G2 414”).
Claim 18 us rejected for the same reasons as claim 4.
Regarding claim 5, Ma teaches the device according to claim 3 (see claim 3 analysis), wherein the second low value is substantially equal to a value of electrostatic potential in an output node of the pixel (Ma, Fig. 4D, The second low value is considered to be substantially equal to the value of P3 410 or FD 404 in Fig. 4D.).
Claim 19 us rejected for the same reasons as claim 5.
Regarding claim 7, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first semiconductor region and the second semiconductor region are doped with the same conductivity type (Ma, Paragraph 0038, “P1 406, P2 408, and P3 410 may be p-type regions formed with one or more p-type dopants”).
Regarding claim 8, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first semiconductor region and the second semiconductor region have a substantially equal dopant concentration (Ma, Paragraph 0038, “in this example, P1 406, P2 408, and P3 410 may also have the same doping concentration”).
Regarding claim 10, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first conductive core and the second conductive core are separated by a portion of the sheath (Ma, Fig. 1-2).
Regarding claim 11, Ma teaches the device according to claim 10 (see claim 10 analysis), wherein the first conductive core and the second conductive core are doped with the same conductivity type (Ma, Paragraph 0033, G1-G3 may be formed with the same polysilicon materials.).
Regarding claim 13, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the pixel is laterally surrounded by an insulated conductive wall (Ma, Figs. 1-2, “pixel 100 may include region 132 that is isolated from substrate 130 by dielectric material 150, at the outer layer surrounding the perimeter of pixel 100”).
Regarding claim 14, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the second conductive core entirely laterally surrounds the second semiconductor region (Ma, Figs. 1-2, G2 114 surrounds P2 108, Paragraph 0034).
Regarding claim 15, Ma teaches the device according to claim 14 (see claim 14 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.), the second conductive core being located between the second semiconductor region and the second portion (Ma, Figs. 1-2, The second conductive core is between the second semiconductor region and the second portion. That is, along a direction from B to B’ on a plane of the second conductive core, the order of elements is FD 104, G2 114 and G1 112.).
Regarding claim 16, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.), the second semiconductor region being laterally surrounded partially by the second conductive core (Ma, Figs. 1-2, Paragraph 0034, The second conductive core fully (and therefore partially) surrounds the second semiconductor region.) and partially by the second portion (Ma, Fig. 1, Fig. 2 (Left Figure), The section of the second portion on the same horizontal plane as the second semiconductor region is considered to be partially surrounding the second semiconductor region.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-11, 13-14 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 2019/0237499 A1) in view of Ma et al. (US 2024/0236525 A1).
Regarding claim 1, Roy teaches an electronic device (Roy, Paragraph 0042, image sensor), comprising:
a pixel (Roy, Fig. 3) including:
a photodiode located in a substrate (Roy, Fig. 3, silicon layer 121 and n-well 147, Paragraphs 0043, 0046 and 0054);
a charge transfer channel comprising a first semiconductor region (Roy, Fig. 3, silicon layer 121b, Paragraph 0049) and a second semiconductor region (Roy, Fig. 3, silicon layer region 139, Paragraph 0049), the second semiconductor region being separated from the photodiode by the first semiconductor region (Roy, Fig. 3, silicon layer region 139 is separated from silicon layer 121 (photodiode) by silicon layer 121b.); and
a trench surrounding the channel, the trench comprising a first conductive core (Roy, Fig. 3, conductive material 143, Paragraph 0050) and an insulating sheath (Roy, Fig. 3, isolation layer 145, Paragraph 0050) which separates the first conductive core from the first and second semiconductor regions, the first conductive core laterally surrounding the first semiconductor region (Roy, Fig. 3, Paragraphs 0049-0051).
However, Roy does not teach a second conductive core and the second conductive core laterally surrounding at least partially the second semiconductor region.
In reference to Ma, Ma teaches a trench surrounding the channel (Ma, Figs. 1-2, dielectric material 150, G1 112, G2 114 and G3 116, Paragraphs 0033-0034), the trench comprising a first conductive core (Ma, Figs. 1-2, G1 112), a second conductive core (Ma, Figs. 1-2, G2 114) and an insulating sheath (Ma, Figs. 1-2, dielectric material 150) which separates the first and second conductive cores from the first and second semiconductor regions, the first conductive core laterally surrounding the first semiconductor region and the second conductive core laterally surrounding at least partially the second semiconductor region (Ma, Figs. 1-2, Paragraph 0034, “G1 112, G2 114, and G3 116 may each have a ring-shape geometry, thus completely enclosing their corresponding modulation regions P1 106, P2 108, and P3 110”).
These arts are analogous since they are both related to pixels with vertical transfer gates. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Roy with the teaching of using a second conductive core for the second semiconductor region as seen in Ma to allow the transfer gates to be controlled separately and allow for greater control of the pixel charge.
Regarding claim 2, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis). However, Roy does not explicitly teach further comprising control circuit for generating control voltages for biasing the first conductive core and the second conductive core.
In further reference to Ma, Ma teaches control circuit (Ma, Fig. 5, row logic and drivers circuit(s) 552, Paragraph 0041) for generating control voltages for biasing the first conductive core and the second conductive core (Ma, Figs. 4-5, Paragraphs 0038-0040).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the explicit teaching of a control circuit as seen in Ma to provide the signals for control of the image sensor.
Regarding claim 3, the combination of Roy and Ma teaches the electronic device according to claim 2 (see claim 2 analysis), wherein the control circuit is configured to:
bias the first conductive core during a pixel integration operation so that electrostatic potentials of the first semiconductor region and the second semiconductor region are at a high value (Roy, Fig. 7A, Paragraph 0076-0077);
bias the first conductive core during a pixel charge transfer operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are, respectively, at a first low value and at a second low value, the first low value being higher than the second low value (Roy, Fig. 7B, Paragraph 0078-0080);
bias the first conductive core during a second step of passage from the pixel charge transfer operation to the pixel readout operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are equal to the high value (Roy, Fig. 7C, Paragraph 0081).
However, the combination of Roy and Ma does not teach bias the second conductive core during a pixel integration operation so that electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are at a high value; bias the second conductive core during a pixel charge transfer operation so that the electrostatic potential of the second semiconductor region is, at the second low value, bias the first conductive core and the second conductive core during a first step of passage from the pixel charge transfer operation to a pixel readout operation so that the electrostatic potential of the first semiconductor region is at the high value and the electrostatic potential of the second semiconductor region is at the second low value; and bias the second conductive core during a second step of passage from the pixel charge transfer operation to the pixel readout operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are equal to the high value (Examiner notes: A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. (see MPEP 2114.II)).
In further reference to Ma, Ma teaches bias the first conductive core and the second conductive core during a pixel integration operation so that electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are at a high value (Ma, Figs. 4A and 4B, Exposure period 432, Paragraph 0038, The electrostatic potentials (potential profile relative to PD 402) of P1 and P2 are high.);
bias the first conductive core and the second conductive core during a pixel charge transfer operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are, respectively, at a first low value and at a second low value, the first low value being higher than the second low value (Ma, Figs. 4A and 4C, Paragraph 0039);
bias the first conductive core and the second conductive core during a first step of passage from the pixel charge transfer operation to a pixel readout operation so that the electrostatic potential of the first semiconductor region is at the high value and the electrostatic potential of the second semiconductor region is at the second low value (Ma, Figs. 4A and 4D, Paragraph 0040); and
bias the first conductive core and the second conductive core during a second step of passage from the pixel charge transfer operation to the pixel readout operation so that the electrostatic potentials of the first semiconductor region and the second semiconductor region are substantially equal and are equal to the high value (Ma, Fig. 4A, End of period 436 where control signals G1-G3 are low.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the teaching of biasing the second conductive core as seen in Ma to control the second semiconductor region and transfer charges generated.
Claim 17 us rejected for the same reasons as claim 3.
Regarding claim 4, the combination of Roy and Ma teaches the device according to claim 3 (see claim 3 analysis), wherein control voltages applied to the first conductive core and the second conductive core by the control circuit for biasing are different at least during a pixel operation (Ma, Fig. 4A, Paragraph 0039, Control signal to G1 and control signal to G2 are different control voltages. Further, “voltages of different values may be applied to G1 412 and G2 414”).
Claim 18 us rejected for the same reasons as claim 4.
Regarding claim 5, the combination of Roy and Ma teaches the device according to claim 3 (see claim 3 analysis), wherein the second low value is substantially equal to a value of electrostatic potential in an output node of the pixel (Roy, Fig. 7B).
Claim 19 us rejected for the same reasons as claim 5.
Regarding claim 6, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the photodiode comprises a third semiconductor region (Roy, Fig. 3, n-well 147) and a fourth semiconductor region (Roy, Fig. 3, silicon layer 121) that are in contact with each other and have opposite doping types, the fourth semiconductor region being in contact with the first semiconductor region (Roy, Fig. 3, Paragraphs 0043, 0046 and 0054, Silicon layer 121 is p-type and n-well 147 Is n-type. Silicon layer 121 is in contact with silicon layer 121b).
Regarding claim 7, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first semiconductor region and the second semiconductor region are doped with the same conductivity type (Roy, Figs. 3 and 5, Paragraph 0068).
Regarding claim 8, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first semiconductor region and the second semiconductor region have a substantially equal dopant concentration (Roy, Figs. 3 and 5, Paragraph 0068, “The doping level in the region 139 may have a varying profile, which decreases in doping level until it reaches a doping level near that of the silicon layer 121 at the boundary of the two layers.”).
Regarding claim 10, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first conductive core and the second conductive core are separated by a portion of the sheath (Ma, Fig. 1-2).
Regarding claim 11, the combination of Roy and Ma teaches the device according to claim 10 (see claim 10 analysis), wherein the first conductive core and the second conductive core are doped with the same conductivity type (Ma, Paragraph 0033, G1-G3 may be formed with the same polysilicon materials.).
Regarding claim 13, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the pixel is laterally surrounded by an insulated conductive wall (Roy, Fig. 3, deep isolation trench 122, conductor, insulator 123, Paragraph 0044).
Regarding claim 14, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the second conductive core entirely laterally surrounds the second semiconductor region (Ma, Figs. 1-2, G2 114 surrounds P2 108, Paragraph 0034).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2024/0236525 A1) in view of Fukuoka (US 2021/0005654 A1).
Regarding claim 9, Ma teaches the device according to claim 1 (see claim 1 analysis). However, Ma does not teach wherein a thickness of the sheath separating the first semiconductor region and the first conductive core is different from a thickness of the sheath separating the second semiconductor region and the second conductive core.
In reference to Fukuoka, Fukuoka teaches wherein a thickness of the sheath (Fukuoka, Figs. 4-7, gate insulating film 122) separating a first semiconductor region (Fukuoka, Figs. 4-5, charge transfer channel 121, Figs. 6-7, charge transfer channel 171, The first semiconductor region is a lower section.) and a conductive core (Fukuoka, Figs. 4-7, gate electrode 123) is different from a thickness of the sheath separating a second semiconductor region (Fukuoka, Figs. 4-7, charge transfer channel 121/171, The second semiconductor region is an upper section.) and the conductive core (Fukuoka, Figs. 4-7, Paragraphs 0081-0092, The thickness of the gate insulating film 122 increases/decreases from the lower section to the upper section.).
These arts are analogous since they are both related to pixels with vertical transfer gates. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Ma with the teaching of changing the sheath thickness as seen in Fukuoka to further facilitate electric charge transfer from the photoelectric conversion unit to the floating diffusion layer (Fukuoka, Paragraph 0083). Further the limitation “wherein a thickness of the sheath separating the first semiconductor region and the first conductive core is different from a thickness of the sheath separating the second semiconductor region and the second conductive core” would be met by increases/decreases the thickness of the sheath.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 2019/0237499 A1) in view of Ma et al. (US 2024/0236525 A1) in view of Fukuoka (US 2021/0005654 A1).
Regarding claim 9, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis). However, the combination of Roy and Ma does not teach wherein a thickness of the sheath separating the first semiconductor region and the first conductive core is different from a thickness of the sheath separating the second semiconductor region and the second conductive core.
In reference to Fukuoka, Fukuoka teaches wherein a thickness of the sheath (Fukuoka, Figs. 4-7, gate insulating film 122) separating a first semiconductor region (Fukuoka, Figs. 4-5, charge transfer channel 121, Figs. 6-7, charge transfer channel 171, The first semiconductor region is a lower section.) and a conductive core (Fukuoka, Figs. 4-7, gate electrode 123) is different from a thickness of the sheath separating a second semiconductor region (Fukuoka, Figs. 4-7, charge transfer channel 121/171, The second semiconductor region is an upper section.) and the conductive core (Fukuoka, Figs. 4-7, Paragraphs 0081-0092, The thickness of the gate insulating film 122 increases/decreases from the lower section to the upper section.).
These arts are analogous since they are both related to pixels with vertical transfer gates. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the teaching of changing the sheath thickness as seen in Fukuoka to further facilitate electric charge transfer from the photoelectric conversion unit to the floating diffusion layer (Fukuoka, Paragraph 0083). Further the limitation “wherein a thickness of the sheath separating the first semiconductor region and the first conductive core is different from a thickness of the sheath separating the second semiconductor region and the second conductive core” would be met by increases/decreases the thickness of the sheath.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2024/0236525 A1) in view of Adkisson et al. (US 2009/0179232 A1).
Regarding claim 12, Ma teaches the device according to claim 1 (see claim 1 analysis). However, Ma does not teach wherein the first conductive core and the second conductive core are made of doped semiconductor materials of opposite types.
In reference to Adkisson et al. (hereafter referred as Adkisson), Adkisson teaches wherein the first conductive core and the second conductive core are made of doped semiconductor materials of opposite types (Adkisson, Figs. 3-4, p-type region 175a/176a and n-type region 175b/176b, Paragraphs 0060-0061).
These arts are analogous since they are both related to pixels multi-gate transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Ma with the use of conductive cores are made of doped semiconductor materials of opposite types as seen in Adkisson since it is a known material for the construction of multi-gate transfer transistors and would produce similar and expected results for transferring charges through a charge transfer channel (Adkisson, Paragraph 0065).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 2019/0237499 A1) in view of Ma et al. (US 2024/0236525 A1) in view of Adkisson et al. (US 2009/0179232 A1).
Regarding claim 12, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis). However, the combination of Roy and Ma does not teach wherein the first conductive core and the second conductive core are made of doped semiconductor materials of opposite types.
In reference to Adkisson et al. (hereafter referred as Adkisson), Adkisson teaches wherein the first conductive core and the second conductive core are made of doped semiconductor materials of opposite types (Adkisson, Figs. 3-4, p-type region 175a/176a and n-type region 175b/176b, Paragraphs 0060-0061).
These arts are analogous since they are both related to pixels multi-gate transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the use of conductive cores are made of doped semiconductor materials of opposite types as seen in Adkisson since it is a known material for the construction of multi-gate transfer transistors and would produce similar and expected results for transferring charges through a charge transfer channel (Adkisson, Paragraph 0065).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2024/0236525 A1) in view of Hiramatsu et al. (US 2023/0403871 A1).
Alternatively, regarding claim 15, Ma teaches the device according to claim 14 (see claim 14 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.).
However, Ma does not teach the second conductive core being located between the second semiconductor region and the second portion.
In reference to Hiramatsu et al. (hereafter referred as Hira), Hira teaches wherein a first conductive core (Hira, Fig. 40, accumulation electrode 37 and drive line LD2) comprises a first portion (Hira, Fig. 40, accumulation electrode 37, Paragraph 0146 and 0237) laterally surrounding a first semiconductor region (Hira, Fig. 40, upper section of semiconductor layer 35 between accumulation electrode 37 (Examiner notes semiconductor layer 35 is mislabeled “34” in Figure 40) and a second portion (Hira, Fig. 40, drive line LD2, Paragraph 0186), a second conductive core (Hira, Fig. 40, transfer gate 11) being located between a second semiconductor region (Hira, Fig. 40, lower section of semiconductor layer 35 between transfer gate 11.) and the second portion (Hira, Fig. 40, Right section of transfer gate 11 is between the second semiconductor region and drive line LD2.).
These arts are analogous since they are both related to pixels with vertical charge transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Ma with the drive line connection layout as seen in Hira since it is a known method of connecting drive lines to gate electrodes in a vertical configuration and would provide similar and expected results for providing drive signals.
Regarding claim 16, Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.), the second semiconductor region being laterally surrounded partially by the second conductive core (Ma, Figs. 1-2, Paragraph 0034, The second conductive core fully (and therefore partially) surrounds the second semiconductor region.).
However, Ma does not teach the second semiconductor region being laterally surrounded partially by the second portion.
Hira teaches wherein a first conductive core (Hira, Fig. 40, accumulation electrode 37 and drive line LD2) comprises a first portion (Hira, Fig. 40, accumulation electrode 37, Paragraph 0146 and 0237) laterally surrounding a first semiconductor region (Hira, Fig. 40, upper section of semiconductor layer 35 between accumulation electrode 37 (Examiner notes semiconductor layer 35 is mislabeled “34” in Figure 40) and a second portion (Hira, Fig. 40, drive line LD2, Paragraph 0186), a second semiconductor region (Hira, Fig. 40, lower section of semiconductor layer 35 between transfer gate 11.) being laterally surrounded partially by a second conductive core (Hira, Fig. 40, transfer gate 11) and partially by the second portion (Hira, Fig. 40, LD2 partially surrounds the right side of the semiconductor region.).
These arts are analogous since they are both related to pixels with vertical charge transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Ma with the drive line connection layout as seen in Hira since it is a known method of connecting drive lines to gate electrodes in a vertical configuration and would provide similar and expected results for providing drive signals.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 2019/0237499 A1) in view of Ma et al. (US 2024/0236525 A1) in view of Hiramatsu et al. (US 2023/0403871 A1).
Alternatively, regarding claim 15, the combination of Roy and Ma teaches the device according to claim 14 (see claim 14 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.).
However, the combination of Roy and Ma does not teach the second conductive core being located between the second semiconductor region and the second portion.
In reference to Hira, Hira teaches wherein a first conductive core (Hira, Fig. 40, accumulation electrode 37 and drive line LD2) comprises a first portion (Hira, Fig. 40, accumulation electrode 37, Paragraph 0146 and 0237) laterally surrounding a first semiconductor region (Hira, Fig. 40, upper section of semiconductor layer 35 between accumulation electrode 37 (Examiner notes semiconductor layer 35 is mislabeled “34” in Figure 40) and a second portion (Hira, Fig. 40, drive line LD2, Paragraph 0186), a second conductive core (Hira, Fig. 40, transfer gate 11) being located between a second semiconductor region (Hira, Fig. 40, lower section of semiconductor layer 35 between transfer gate 11.) and the second portion (Hira, Fig. 40, Right section of transfer gate 11 is between the second semiconductor region and drive line LD2.).
These arts are analogous since they are all related to pixels with vertical charge transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the drive line connection layout as seen in Hira since it is a known method of connecting drive lines to gate electrodes in a vertical configuration and would provide similar and expected results for providing drive signals.
Alternatively, regarding claim 16, the combination of Roy and Ma teaches the device according to claim 1 (see claim 1 analysis), wherein the first conductive core comprises a first portion (Ma, Fig. 1, Fig. 2 (Left Figure), G1 112, Paragraph 0036, The first portion is the horizontal portion of G1 112.) laterally surrounding the first semiconductor region and a second portion (Ma, Fig. 1, Fig. 2 (Left Figure), Paragraph 0036, The second portion is the vertical portion of G1 112.), the second semiconductor region being laterally surrounded partially by the second conductive core (Ma, Figs. 1-2, Paragraph 0034, The second conductive core fully (and therefore partially) surrounds the second semiconductor region.).
However, the combination of Roy and Ma does not teach the second semiconductor region being laterally surrounded partially by the second portion.
Hira teaches wherein a first conductive core (Hira, Fig. 40, accumulation electrode 37 and drive line LD2) comprises a first portion (Hira, Fig. 40, accumulation electrode 37, Paragraph 0146 and 0237) laterally surrounding a first semiconductor region (Hira, Fig. 40, upper section of semiconductor layer 35 between accumulation electrode 37 (Examiner notes semiconductor layer 35 is mislabeled “34” in Figure 40) and a second portion (Hira, Fig. 40, drive line LD2, Paragraph 0186), a second semiconductor region (Hira, Fig. 40, lower section of semiconductor layer 35 between transfer gate 11.) being laterally surrounded partially by a second conductive core (Hira, Fig. 40, transfer gate 11) and partially by the second portion (Hira, Fig. 40, LD2 partially surrounds the right side of the semiconductor region.).
These arts are analogous since they are all related to pixels with vertical charge transfer transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Roy and Ma with the drive line connection layout as seen in Hira since it is a known method of connecting drive lines to gate electrodes in a vertical configuration and would provide similar and expected results for providing drive signals.
Conclusion
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/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639
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