DETAILED ACTION
Re Application No. 19/178864, this action responds to the amended claims dated 07/27/2026.
At this point, claims 1-2, 7, 16-18, and 22 have been amended. Claims 6, 11-15, and 21 have been cancelled. New claims 23-24 have been added. Claims 1-5, 7-10, and 16-20, and 22-24 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Examiner notes Applicant’s amended claims dated 07/27/2026. In view of the amendment cancelling claim 21, Examiner’s prior objection has been rendered moot, and is accordingly withdrawn.
Double Patenting
Examiner notes Applicant’s arguments dated 07/27/2026. Applicant has not specifically disputed the applicability of the double patenting rejections, but has requested clarification as to which Koufaty reference is being referred to. Accordingly, Examiner confirms that the rejection refers to Koufaty et al (US 2019/0018806 A1), as has been cited elsewhere in this action as prior art.
Examiner’s rejections of claims 1, 2, 3-5, 7-8, 16-18, 19-20, and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 1, 7-8, 13, 19-20, 2, and 13 of U.S. Patent No. 12293090 in view of Koufaty, has been maintained.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Examiner notes Applicant’s amended claims dated 07/27/2026. In view of the amendment amending claim 2 and cancelling claim 21, Examiner’s prior rejections under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-10, 16-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Koufaty et al (US 2019/0018806 A1).
Re claim 1, Koufaty discloses the following:
A storage device, comprising: a storage for a data (Fig. 1, system memory 130);
a controller to manage access to the data in the storage; and (Fig. 1, coherence controller 116; ¶ 44-4545 and 65). The system contains a coherence controller to manage coherence for memory, which in turn involves memory access (Fig. 1; ¶ 44). Additionally, there are accelerator memory controllers and CPU memory controllers (¶ 45). Furthermore, the computing architecture may include common components such as memory controllers (¶ 65);
a mechanism to manage an operating mode for an address in the storage based at least in part on a device accessing a second address in the storage, the address storing a data, the second address storing a second data, the second address associated with a second operating mode (¶ 34 and 53). A host bias mode may be switched to device bias mode, or vice versa (manage an operating mode) based on the device or host, respectively, accessing a memory address (¶ 53). The granularity of the bias information may be entire memory regions or address ranges; accordingly, in the case where an entire memory region/range is associated with a single bias indicator, an access to one address (second address) in this region/range would cause the bias indicator to be changed (managed) for other addresses (the address) (¶ 34);
the operating mode including one of a first mode and a second mode, the second operating mode including one of the first mode and the second mode (Figs. 5A-5B; ¶ 13, 34, and 46-51). Applicant has not explicitly defined “first” and “second” operating modes. It is further noted that both the first and second operating mode each include one of the first and second modes, and are not explicitly required to be different from each other. Accordingly, Koufaty discloses switching between a host bias mode (first mode) and a device bias mode (second mode), wherein in the host bias mode, requests are routed through a local cache coherence element of the host processor, while in device bias mode, this is skipped in favor of directly servicing requests at memory (Figs. 5A-5B; ¶ 13, 34, and 46-51). In some instances, this can be managed by using bias table bits to indicate which mode to use for particular regions of memory (chunks) (¶ 50). Furthermore, the bias indicator may specify particular address ranges as being biased towards the first or second mode (¶ 34).
Koufaty discloses multiple embodiments for specifying bias modes; accordingly, it is not explicitly stated whether each of these elements appears in a common embodiment. Nonetheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine the embodiments of Koufaty to yield the claimed invention, as it would merely be making the embodiments integral (MPEP § 2144.04(V)(B)).
Re claim 2, Koufaty discloses the device of claim 1, and further discloses that the mechanism to manage the operating mode for the address in the storage is configured to issue a request to a host processor for the data stored at the address in the storage based at least in part on the operating mode for a chunk of the data in the storage being switched to the second mode (¶ 49). A flush and/or snoop-invalidate (invalidate request or back invalidate request) message is sent to the host processor when the bias mode for the requested chunk is in device bias mode (second mode).
Re claim 3, Koufaty discloses the device of claim 1, and further discloses that the mechanism to manage the operating mode for the address in the storage is configured to manage the operating mode for the address in the storage based at least in part on a fabric controller accessing the address in the storage (¶ 36). The bus logic (fabric controller) communicates over the interconnect using a fabric-based protocol, and includes operations such as memory access (accessing the address in the storage).
Re claim 4, Koufaty discloses the device of claim 1, and further discloses that the mechanism to manage the operating mode for the address in the storage is further configured to manage the operating mode for the address in the storage based at least in part on a use of the data in the storage by an application (¶ 53 and 46). A bias transition for a memory location (address) can be initiated (managed) based on an accelerator access to host bias mode memory, or host access to device bias mode memory (¶ 53). The software application associated with the CPU may issue a request or memory operation to the accelerator memory (¶ 46).
Re claim 5, Koufaty discloses the device of claim 1, and further discloses that the mechanism to manage the operating mode for the address in the storage is further configured to manage the operating mode for the address in the storage based at least in part on a workload of an application accessing the address in the storage (¶ 53, 59, and 64). The bias (operating mode) may be switched in response to accessing a memory location (address) (¶ 53). The software application associated with the CPU may issue a request or memory operation to the accelerator memory (¶ 46).
The host application may submit work (workload of an application), which may involve memory accesses (¶ 59).
Re claim 8, Koufaty discloses the device of claim 1, and further discloses that the mechanism to manage the operating mode for the address in the storage includes a snoop filter including an entry for the address in the storage as accessed by an application (¶ 34). The bias table may operate as a snoop filter, with indicators (entries) for each chunk of data. Those chunks of data may be associated with addresses (¶ 34). Memory may be accessed by an application (¶ 53 and 64).
Re claim 9, Koufaty discloses the device of claim 8, and further discloses the following:
the entry for the address in the storage identifies that address in the storage is in the first mode; and (¶ 34). The bias table entry indicates whether data corresponding to address ranges are in a first mode or second mode;
the mechanism to manage the operating mode for the address in the storage is further configured to change the operating mode to the second mode based at least in part on the application executing by a processor associated with the storage device (¶ 53 and 64). The bias transition (operating mode change) may be initiated by a device accessing host biased regions, or a host accessing device biased regions. The memory accesses may be performed by an application (¶ 53 and 64).
Re claim 10, Koufaty discloses the device of claim 8, and further discloses the following:
the entry for the address in the storage identifies that address in the storage is in the second mode; and (¶ 34). The bias table entry indicates whether data corresponding to address ranges are in a first mode or second mode;
the mechanism to manage the operating mode for the address in the storage is further configured to change the operating mode to the first mode based at least in part on the application executing by a host processor (¶ 53 and 64). The bias transition (operating mode change) may be initiated by a device accessing host biased regions, or a host accessing device biased regions. The memory accesses may be performed by an application (¶ 53 and 64).
Re claim 16, Koufaty discloses the following:
receiving, at a storage device, a request from a device to access an address in a storage of the storage device, the address storing data; and (Figs. 5A-5B; ¶ 34 and 51). Requests may originate in either the host or the device (storage device), and may be serviced locally, or forwarded to be received by the device/host respectively, depending on the operating mode (Figs. 5A-5B; ¶ 51). Data may be associated with address ranges (¶ 34);
updating an operating mode for the address in the storage of the storage device based at least in part on the request; and (¶ 53). An operating mode may be changed (updated) based on a request to access data, such as by a host attempting to access device-biased data, and vice versa;
updating a second operating mode for a second address in the storage of the storage device based at least in part on the request (¶ 34 and 53). As noted above, the operating mode may be changed (updated) from host to device bias, or vice versa, based on access to an address (¶ 53). Since the granularity of the bias information may include a memory region or range including multiple addresses (¶ 34), changing the operating mode for one address in that region/range would also have the effect of changing the operating mode for the other addresses in that region/range.
Koufaty discloses multiple embodiments for specifying bias modes; accordingly, it is not explicitly stated whether each of these elements appears in a common embodiment. Nonetheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine the embodiments of Koufaty to yield the claimed invention, as it would merely be making the embodiments integral (MPEP § 2144.04(V)(B)).
Re claim 17, Koufaty discloses the method of claim 16, and further discloses receiving, at the storage device, the request from the device to access the address in the storage of the storage device includes receiving, at the storage device, the request to access the address in the storage of the storage device from an application executing by a host processor; updating the operating mode for the address in the storage of the storage device based at least in part on the request includes updating the operating mode for the address in the storage device to a first mode (¶ 53 and 64). When a device receives a host request for data that is device-biased, the device may initiate a transition to update the mode to be host-biased mode (first mode) (¶ 53). The requests may come from applications (¶ 53 and 64).
Re claim 18, Koufaty discloses the method of claim 16, and further discloses receiving, at the storage device, the request from the device to access the address in the storage of the storage device includes receiving, at the storage device, the request to access the address in the storage of the storage device from an application executing by a processor associated with the storage device; and updating the operating mode for the address in the storage of the storage device based at least in part on the request includes updating the operating mode for the address in the storage device to a second mode (¶ 53 and 64). When a device receives a device request for data that is host-biased, the device may initiate a transition to update the mode to be device-biased mode (second mode) (¶ 53). The requests may come from applications (¶ 53 and 64).
Re claim 22, Koufaty discloses the method of claim 16, and further discloses that receiving, at the storage device, the request from the device to access the address in the storage device includes receiving, at the storage device, the request to access the address in the storage of the storage device from a fabric controller (Figs. 5A-5B; ¶ 34 and 36). The accelerator (storage device) may receive requests (Figs. 5A-5B) for data corresponding to an address (¶ 34). The bus logic (fabric controller) communicates over the interconnect using a fabric-based protocol, and includes operations such as memory access (accessing the address in the storage) (¶ 36).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Tune et al (US 2016/0062893 A1).
Re claim 7, Koufaty discloses the device of claim 1, and further discloses that the data includes a first page; the second data includes a second page; and the mechanism to manage the operating mode for the address in the storage is further configured to manage the operating mode for the address in the storage based at least in part on the second page […related to] the first page (¶ 34 and 53). Koufaty discloses managing the operating mode based on accessing memory (¶ 53), and further discloses that the granularity for a bias indicator can be a range of memory, which may include multiple addresses (first/second address) (¶ 34); however, it does not explicitly disclose whether the range of memory must be contiguous.
Tune discloses managing an operating mode for the address in the storage based at least in part on the second page being adjacent to the first page (¶ 74). The snoop filter is associated with an address range which is contiguous, i.e. first and second pages are adjacent.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the address range bias indicators of Koufaty to utilize contiguous address ranges, as in Tune, because it would be applying a known technique to improve a similar device in the same way. Koufaty discloses tracking bias indicators for address ranges. Tune also discloses tracking snoop filtering (bias indicator) for address ranges, which has been improved in a similar way to the claimed invention, to utilize contiguous address ranges. It would have been obvious to one having ordinary skill in the art (AIA ) to modify the address ranges of Koufaty to be contiguous, so that contiguous addresses are managed together, as in Tune, because it would yield a predictable improvement to performance by making use of temporal locality (i.e. data located near accessed data is more likely to be accessed as part of a sequential access).
Claim 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Hoover et al (US 2006/0080508 A1).
Re claim 19, Koufaty discloses the method of claim 16, but does not specifically disclose modified vs unmodified status.
Hoover discloses sending a request for the address in the storage of the storage device from the storage device to the host processor based at least in part on the address in the storage of the storage device is unmodified by the host processor (¶ 48). When the snoop filter evicts an entry for data, the CPU (host processor) sends a request to invalidate its cached copy if the copy is unmodified.
It would have been obvious to one having ordinary skill in the art before the
effective filing date of the claimed invention (AIA ) to modify the snoop filter of Koufaty to
invalidate cached copies based on modified status, as in Hoover, because it would be
applying a known technique to improve a similar device in the same way. Koufaty
discloses a snoop filter which tracks whether data should be serviced at a host cache.
Hoover also discloses a snoop filter, which has been improved in a similar way to the
claimed invention, to invalidate/cast out cached data based on modified status. It would
have been obvious to one having ordinary skill in the art (AIA ) to modify the snoop filter
Koufaty to base invalidation/casting on modified status, as in Hoover, because it would
yield the predictable improvement of ensuring cache coherence.
Re claim 20, Koufaty discloses the method of claim 16, but does not specifically disclose modified vs unmodified status.
Hoover discloses sending a request for the address in the storage of the storage device from the storage device to the host processor based at least in part on the address in the storage of the storage device is modified by the host processor (¶ 48). When the snoop filter evicts an entry for data, the CPU (host processor) casts out (back-invalidates) its cached copy if the copy is modified.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Koufaty and Hoover, for the reasons noted in claim 19 above.
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Nakanishi et al (US 2007/0186048 A1).
Re claim 23, Koufaty discloses the device of claim 1; moreover, Koufaty would have the effect that flipping the bias from host to device bias, or vice versa, would be preparation for a subsequent access to another memory address in the address range to be serviced. It is further noted that the limitation “in expectation of the device accessing the address” is very broad, as it does not positively recite doing anything in particular, such as actually predicting a subsequent access, nor does it place any limits on when this would be expected to occur (for example, within a time period or certain number of subsequent instructions). Accordingly, merely flipping the address range from host to device bias, or vice versa, could arguably broadly be considered “in expectation of” a future access, as it is preparing for that possibility by moving the data closer to the biased device. However, as this particular intent is not explicitly stated, in the interest of furthering compact prosecution, Examiner has provided Nakanishi.
Nakanishi discloses that the mechanism to manage the operating mode for the address in the storage is configured to manage the operating mode for the address in the storage in expectation of the deice accessing the address in the storage based on the device accessing the second address in the storage (¶ 101). Predictive prefetching is performed for a range of addresses, such that when a first access to an address is detected, it is predicted (expected) that additional sequential addresses in an address range will also be accessed, and are thus prefetched as well.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) that the address ranges of Koufaty could be associated with predicted (expected) sequential access, as in Nakanishi, because Nakanishi suggests that prefetching the additional addresses of the address range for a predicted sequential access would allow for the prefetching to be performed more efficiently, and eliminate penalties in loading data from memory (¶ 35).
Re claim 24, Koufaty discloses the method of claim 16; see Examiner’s comments re claim 23 above for more detail.
Nakanishi discloses that updating the second operating mode for the second address in the storage in the storage device based at least in part on the request includes updating the second operating mode for the second address in the storage of the storage device in expectation of the device accessing a second chunk of the data in the storage of the storage device (¶ 101). See claim 23 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Koufaty and Nakanishi, for the reasons noted in claim 23 above.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-5, 7-10, 16-20, and 22-24 filed on 07/27/2026 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claims 1 and 16, Applicant argues that the amended claims are not obvious over Koufaty, for 3 reasons.
First, in Applicant’s “General Remarks”, Applicant argues that it was improper for Examiner to have applied form paragraph ¶ 7.06, arguing that 1) the form paragraph does not apply, as the Applicant has not claimed pre-AIA priority, and 2) “Applicant does not believe that it is proper to change the statutory basis between 35 USC § § 102 and 103 without the new rejection being a new ground for rejection”. In response, Applicant’s first argument has been fully considered, but is not deemed persuasive. Re Applicant’s first concern, it is noted that the form paragraph comment merely states that it must be used for an application which claims pre-AIA priority, not that it cannot be used in other situations. Examiner has made rejections under the AIA version of 35 USC 103, and agrees that it is unlikely that there will be any issue of inadvertently referencing the wrong version of this statute; however, that does not make this form paragraph improper, as it is merely a disclaimer for a potential situation that could occur. Re Applicant’s second concern, this appears to reflect a misinterpretation of the form paragraph. It states “any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status”. Changing a 102 rejection to a 103, or vice versa, would not be supported, as this would not be the same rational supporting the rejection. Rather, this refers to an inadvertent application of the pre-AIA version of 35 USC § 102 instead of the AIA version of 35 USC 102, when the rejection would be the same under either version.
Second, Applicant argues that Koufaty does not disclose that the cache coherence controller manages access to the data. In response, Applicant’s first argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, the cache coherence controller does manage access to the data, as it at the very least sends memory access messages to the CPU and accelerator (¶ 45). Second, even assuming, arguendo, that it did not do so, several other components which may be considered “controllers” are also involved in managing memory access. For example, the memory agents, which are components of the CPU and accelerator, and may thus be considered “controllers”, manages access to memory (¶ 23). Furthermore, the CPU and accelerator each have their own memory controllers, which do manage access to memory (¶ 45).
Third, Applicant argues that Koufaty does not disclose that an operating mode of one address might be managed based on another data being accessed. More specifically, Applicant argues that the bias indicator of Koufaty manages an entire unit, and thus it is not possible to have different addresses with different operating modes. In response, Applicant’s third argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, Applicant has not actually affirmatively claimed that the first and second operating modes must be different from one another. In fact, claim 1 explicitly claimed that both the first and second operating modes are “including one of a first mode and a second mode”; accordingly, both the first and second operating modes could be chosen to be the first mode, or both be the second mode, or one could be the first and one could be the second mode. Second, since the operating modes are being “managed” they can be changed, and thus addresses may be associated with different operating modes at different times. For instance, prior to the bias being flipped to host bias, a memory range/region may be in the operating mode of device bias.
Re claim 3, Applicant argues that Koufaty does not disclose managing the operating mode is “based at least in part on a fabric controller accessing the address in the storage”. In response, Applicant’s argument has been fully considered, but is not deemed persuasive. The processor and logic device are capable of transferring memory access information over link 115, which may include various fabric-based protocols. While the exact structure of the logic managing those protocols is not explicitly disclosed, it would have been obvious to one having ordinary skill in the art that such protocols would be implemented in some sort of logic, which can be considered a “fabric controller”.
Re claim 4, Applicant argues that the management of Koufaty is not “based at least in part on a use of the data in the storage by an application”. In response, Applicant’s argument has been fully considered, but is not deemed persuasive. The software application associated with the CPU may issue a request or memory operation to the accelerator memory (¶ 46).
Re claim 5, Applicant argues that the management of Koufaty is not “based at least in part on a workload of an application accessing the address in the storage.” In response, Applicant’s argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, Examiner does not interpret “a workload of an application accessing the address in the storage” as necessarily referring to the access actually occurring; rather, it may be interpreted as being a description of what the workload is. In other words, the workload may refer to the set of steps that are to be undertaken, and not necessarily to the steps being performed. Second, even assuming, arguendo, that this were limited to the narrower interpretation argued by Applicant, the limitation “manage the operating mode” does not necessarily need to refer to a single step that must occur at a discrete time, but rather may be considered as an ongoing management process; the operating mode is continuously “managed” and may switch back and forth multiple times.
Re claim 8, Applicant argues that Koufaty does not disclose that “the mechanism that manages the operating mode for the address includes a snoop filter”, as Koufaty allegedly only teaches that the bias table includes a snoop filter. In response, Applicant’s argument has been fully considered, but is not deemed persuasive. The mechanism that manages the operating mode does so at least in part by using the bias table (i.e. by setting/clearing bias table bits, and consulting the bias table to determine the operating mode), and the bias table includes a snoop filter.
Re new claims 23-24, Applicant is directed to Examiner’s rejections above.
Re claims 2-5, 7-10, 17-20, and 22-24, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1 and 16 above, respectively. Accordingly, Applicant is directed to Examiner’s comments regarding claims 1 and 16 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 07/27/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Per the instant office action, claims 1-20 have received an action on the merits and are subject to a final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132
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