DETAILED ACTION
This office action is in response to the application filed on 04/15/2025. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Drawing
The drawing submitted on 04/15/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/15/2025 and 08/04/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 15-16 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by INOUE (US Patent or PG Pub. No. 20160344302, hereinafter ‘302).
Claim 1, ‘302 teaches an apparatus (e.g., see Fig. 1-10) comprising: an input terminal configured to receive an input signal (e.g., VAC1_DET, see Fig. 3); a first comparator (e.g., ZC_CMP1) coupled to the input terminal and configured to compare the input signal to a first threshold (e.g., VZC1) and to generate a first signal (e.g., ZC_DET1) in response to the input signal exceeding the first threshold; a first circuit (e.g., 202, 210) coupled to the first comparator and configured to initiate a first interval (e.g., τ) in response to the first signal and to provide a control signal (e.g., the output of 230) after expiration of the first interval (e.g., through 202, see Fig. 3, 6); and a second comparator (e.g., ADJ_CMP1) coupled to the input terminal and configured to compare the input signal to a second threshold (e.g., VTH1) and to generate a second signal (e.g., VF_DET1) based on a comparison between the input signal and the second threshold; wherein the first circuit is further configured to adjust the first interval based at least on the second signal (e.g., see [0026]-[0030];[0141]-[142]).
Claim 2, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the input signal comprises an alternating current (AC) component (e.g., the AC input at AC1 and AC2, see Fig. 3).
Claim 3, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that further comprising a driver (e.g., 208) coupled to the first circuit and configured to receive the control signal (e.g., see Fig. 3).
Claim 4, ‘302 teaches the limitations of claim 3 as discussed above. It further teaches that further comprising a first transistor (e.g., M1) coupled to the driver, the driver being configured to activate the first transistor in response to the control signal (e.g., see Fig. 3).
Claim 5, ‘302 teaches the limitations of claim 4 as discussed above. It further teaches that further comprising a second transistor (e.g., M4 or M2) coupled in parallel with the first transistor, the second transistor being configured to be activated after the first transistor (e.g., M2 being activated by OUT2 in the next negative half cycle of the next AC cycle, see Fig. 3, 4).
Claim 6, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the second threshold (VTH1) is greater than a reference voltage associated with a rectified output (e.g., the level of VTH1 being reference to the GND of the rectified output, see Fig. 3).
Claim 7, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the first circuit is configured to increase the first interval in response to the second signal indicating that the input signal is below the second threshold (e.g., see [0101[0102]).
Claim 8, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the first circuit is configured to decrease the first interval in response to the second signal indicating that the input signal exceeds the second threshold (e.g., see [0101[0102], [0141][0142]).
Claim 9, ‘302 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the second threshold is greater than the first threshold (e.g., S104, see [0142], Fig. 7).
Claim 10, ‘302 teaches an apparatus (e.g., see Fig. 1-10) comprising:
an input terminal configured to receive an input signal (e.g., VAC1_DET, see Fig. 3); a first comparator (e.g., ZC_CMP1) coupled to the input terminal and configured to compare the input signal to a first threshold (e.g., VZC1) and to generate a first signal (e.g., ZC_DET1) in response to the input signal exceeding the first threshold; a first circuit (e.g., 202, 210) coupled to the first comparator and configured to initiate a first interval a first interval (e.g., T) in response to the first signal; and a second comparator (e.g., ADJ_CMP1) coupled to the input terminal and configured to compare the input signal to a second threshold (e.g., VTH1) and to generate a second signal (e.g., VF_DET1) based on a comparison between the input signal and the second threshold, the second threshold being greater than the first threshold (e.g., S104, see [0142], Fig. 7); wherein the first circuit is further configured to adjust the first interval based at least on the second signal (e.g., S106, see [0026]-[0030];[0141]-[142], Fig. 7).
Claim 11, ‘302 teaches the limitations of claim 10 as discussed above. It further teaches that further comprising a driver (e.g., 208) coupled to the first circuit, the first circuit being configured to provide a control signal (e.g., the output of 230) to the driver after expiration of the first interval (e.g., through 202, see Fig. 3, 6).
Claim 12, ‘302 teaches the limitations of claim 11 as discussed above. It further teaches that further comprising a first transistor (e.g., M1) coupled to the driver, the driver being configured to activate the first transistor in response to the control signal (e.g., see Fig. 3).
Claim 13, ‘302 teaches the limitations of claim 10 as discussed above. It further teaches that wherein the second threshold is greater than a reference voltage associated with a rectified output (e.g., the level of VTH1 being reference to the GND of the rectified output, see Fig. 3).
Claim 14, ‘302 teaches the limitations of claim 10 as discussed above. It further teaches that wherein the first circuit is configured to decrease the first interval in response to the second signal indicating that the input signal exceeds the second threshold (e.g., see [0101[0102], [0141][0142]).
Claim 15, ‘302 teaches the limitations of claim 10 as discussed above. It further teaches that wherein the first circuit is configured to increase the first interval in response to the second signal indicating that the input signal is below the second threshold (e.g., see [0101[0102]).
Claim 16, ‘302 teaches an apparatus (e.g., see Fig. 1-10) comprising:
an input terminal configured to receive an input signal (e.g., VAC1_DET, see Fig. 3); a first circuit (e.g., 202, 210) coupled to the input terminal and configured to provide a control signal (e.g., the output of 230) based at least on the input signal (e.g., see Fig. 3, 6); a driver (e.g., 208) coupled to the first circuit and configured to receive the control signal (e.g., see Fig. 3, 4, 6); a first transistor (e.g., M1) coupled to the driver, the driver being configured to activate the first transistor in response to the control signal; and a second transistor (e.g., M4 or M2) coupled in parallel with the first transistor, the second transistor being configured to be activated after the first transistor (e.g., M2 being activated by OUT2 in the next negative half cycle of the next AC cycle, see Fig. 3, 4).
Claim 17, ‘302 teaches the limitations of claim 16 as discussed above. It further teaches that wherein the input signal comprises an alternating current (AC) component (e.g., the AC input at AC1 and AC2, see Fig. 3).
Claim 18, ‘302 teaches the limitations of claim 16 as discussed above. It further teaches that further comprising a first comparator (e.g., ZC_CMP1) coupled to the input terminal and the first circuit, the first comparator being configured to compare the input signal to a first threshold (e.g., VZC1) and to generate a first signal (e.g., ZC_DET1) in response to the input signal exceeding the first threshold.
Claim 19, ‘302 teaches the limitations of claim 18 as discussed above. It further teaches that wherein the first circuit is configured to initiate a first interval (e.g., τ) in response to the first signal and to generate the control signal after expiration of the first interval (e.g., through 202, see Fig. 3, 6).
Claim 20, ‘302 teaches the limitations of claim 16 as discussed above. It further teaches that further comprising a second comparator (e.g., ADJ_CMP1) coupled to the input terminal and configured to compare the input signal to a second threshold (e.g., VTH1) and to generate a second signal (e.g., VF_DET1) based on a comparison between the input signal and the second threshold (e.g., see Fig. 3, 4, 6).
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication US 20240030832 A1 discloses a synchronous Bridge rectifier with adaptive turn-off circuit.
US Patent Application Publication US 20130235635 A1 discloses a synchronous Bridge rectifier with comparator circuits for timing generation of on/off control of the power transistors of the synchronous Bridge rectifier.
US Patent Application Publication US 20150117076 A1 discloses a synchronous Bridge rectifier and control method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
