DETAILED ACTION
Status of Application
Claims 1-18 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 16 of U.S. Patent No. 12,307,251 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting one of the independent claims from the instant application and U.S Patent for the table below.
Instant Application
U.S. Patent No. 12,307,251 B2
1. A device comprising:
a source register including n lanes to store n elements, in which a first element of the n elements is stored in a first lane of the n lanes and each successive element of the n elements is stored in a respective successive lane of the n lanes, wherein n is a positive integer of 4 or greater;
a destination register including n lanes; and
a processor to execute a reverse instruction in a single cycle of the processor to:
place the first element in the nth lane of the destination register, and
place each successive element of the n elements in a respective preceding lane of the destination register, including placing the nth element of the n elements in the first lane of destination register.
A processor comprising:
an instruction fetch unit configured to receive a vector reverse instruction that specifies a single vector reverse operation; and
a datapath coupled to the instruction fetch unit that includes:
a register file that includes a source register including a set of n lanes configured to store a first vector that includes a set of n elements, in which a first element of the set of n elements is stored in a first lane of the set of n lanes and each succeeding element of the set of n elements is stored in a respective succeeding lane of the set of n lanes, and a destination register including a set of n lanes, wherein n is a positive integer of 4 or greater;
wherein the processor is configured to, based on the vector reverse instruction:
reverse an order of the set of n elements of the first vector to produce a second vector that includes the set of n elements; and
cause the second vector to be stored in the destination register, in which the first element of the set of n elements of the second vector is stored in the nth lane of the destination register and each succeeding element of the second vector is stored in a respective preceding lane of the destination register,
wherein the vector reverse instruction is executed in a single operation
Claims 2-8, 13-14, and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-8, 17-18, and 20, respectively, of U.S. Patent No. 12,307,251 B2.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,307,251 B2.
Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9 of U.S. Patent No. 11,900,112 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Claims 2-8, 13-14, and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-8, 17-18, and 20, respectively, of U.S. Patent No. 12,307,251 B2.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12,307,251 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 5, 12, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Corbal et al (hereinafter Corbal), US 20160179529 A1, in view of Morad et al (hereinafter Morad), US 20080240093 A1.
Referring to claims 1 and 12, taking claim 1 as exemplary, Corbal discloses a device comprising:
a source register [fig. 20, source register 2001] including n lanes [fig. 20, see the lanes separated by dashed lines below,
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to store n elements [paragraph 164, “input vector data to be reversed/swapped”; see elements 7-0 in fig. 20 of SRC 2001], in which a first element [fig. 20, element “7”] of the n elements is stored in a first lane of the n lanes [see marked up figure above, “Ln1”] and each successive element of the n elements is stored in a respective successive lane of the n lanes [see marked up figure above, succeeding elements 6-0 stored in respective successive lanes Ln2-Ln8], wherein n is a positive integer of 4 or greater [in this case, n=8];
a destination register including n lanes [fig. 20, DST register 2004 with eight lanes]; and
a processor to execute a reverse instruction in processor [paragraph 164, “a vector bit reversal instruction”] to:
place the first element in the nth lane of the destination register [fig. 20, see element “7” placed in 8th lane of DST 2004,
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place each successive element of the n elements in a respective preceding lane of the destination register, including placing the nth element of the n elements in the first lane of destination register [see marked up figure 20 above; succeeding element 6 stored in preceding lane 7; succeeding element 5 stored in preceding Ln 6, etc].
Corbal does not explicitly disclose execute a reverse instruction in a single cycle.
However, Morad discloses executing a reverse instruction in a single cycle [paragraph 167, A bit-reverse instruction: a single cycle instruction, which reverses a bit order of the lowest N bits of a first GPR, and stores a result in a second GPR].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Morad in the device of Corbal to implement a reverse instruction in a single cycle, in order to provide a speedy and efficient unit to perform simultaneous multiplexing and de-multiplexing, and even de-multiplex more than one input stream and multiplex more than one output stream simultaneously [Morad, paragraph 102].
Referring to claims 4 and 16, taking claim 4 as exemplary, the modified Corbal discloses the device of claim 1, wherein the reverse instruction specifies a size of each element of the n elements, in which the size of each element is a same number of bits [Corbal, paragraphs 35, 46, “Data element width field 164”].
Referring to claims 5 and 17, taking claim 5 as exemplary, the modified Corbal discloses the device of claim 4, wherein the reverse instruction specifies the size of each element of the n elements as one of a byte, a half-word, a word, and a double word [Corbal, paragraphs 35, 46, vector friendly instruction format; “8 bit (1 byte) data element widths”; “alternative embodiments may support more, less and/or different vector operand sizes”].
Claim(s) 2-3, 6-8, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Corbal, in view of Morad, as applied to claims 1 and 12 above, and further in view of Anderson et al (hereinafter Anderson), US 20170115989 A1.
Referring to claim 2, the modified Corbal does not explicitly disclose the device of claim 1, wherein the reverse instruction specifies whether the processor is permitted to execute the reverse instruction and another instruction in parallel.
However, Anderson discloses wherein the reverse instruction specifies whether the processor is permitted to execute the reverse instruction and another instruction in parallel [paragraph 76, “execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bit 0 of the 32-bit wide slot. The p bit determines whether an instruction executes in parallel with a next instruction”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, wherein the reverse instruction specifies whether the processor is permitted to execute the reverse instruction and another instruction in parallel, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 3, the modified Corbal does not explicitly disclose the device of claim 1, wherein the processor includes multiple datapaths, and the reverse instruction specifies a particular datapath, of the multiple datapaths, to perform the reverse instruction.
However, Anderson discloses wherein the processor includes multiple datapaths, and the reverse instruction specifies a particular datapath, of the multiple datapaths, to perform the reverse instruction [fig. 1, datapaths 116, 115; paragraphs 38-39, “Instruction dispatch unit 112 directs each instruction to its target functional unit”, “One part of the dispatch task of instruction dispatch unit 112 is determining whether the instruction is to execute on a functional unit in scalar datapath side A 115 or vector datapath side B 116”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, wherein the processor includes multiple datapaths, and the reverse instruction specifies a particular datapath, of the multiple datapaths, to perform the reverse instruction, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 6, the modified Corbal does not explicitly disclose the device of claim 1, further comprising:
a register file that includes a plurality of registers including the source register and the destination register;
wherein the reverse instruction specifies the source register and the destination register from among the plurality of registers in the register file.
However, Anderson discloses a register file that includes a plurality of registers including the source register and the destination register [Anderson, paragraph 55, “The two operands are each recalled from an instruction specified register in either global vector register file 231, L2/S2 local register file 232 or predicate register file 234”; “The result may be written into an instruction specified register of global vector register file 231, L2/S2 local register file 222, M2/N2/C local register file 233 or predicate register file 234”];
wherein the reverse instruction specifies the source register and the destination register from among the plurality of registers in the register file [Anderson, paragraph 55, “The two operands are each recalled from an instruction specified register in either global vector register file 231, L2/S2 local register file 232 or predicate register file 234”; “The result may be written into an instruction specified register of global vector register file 231, L2/S2 local register file 222, M2/N2/C local register file 233 or predicate register file 234”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, a register file that includes a plurality of registers including the source register and the destination register; wherein the reverse instruction specifies the source register and the destination register from among the plurality of registers in the register file, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 7, the modified Corbal discloses the device of claim 3, further comprising:
an instruction fetch unit configured to obtain the reverse instruction [Anderson, fig. 1, element 111]; and
an instruction decoder coupled to the instruction fetch unit and the particular datapath [Anderson, fig. 1, element 113].
Referring to claim 8, the modified Corbal does not explicitly disclose the device of claim 1, further comprising:
a level one cache coupled to the processor;
a level two cache coupled to the level one cache; and
a streaming engine coupled between the level two cache and the processor in parallel with the level one cache.
However, Anderson discloses a level one cache coupled to the processor [fig. 1, processor 110 and level one cache 123];
a level two cache [fig. 1, level two cache 130] coupled to the level one cache; and
a streaming engine [fig. 1, streaming engine 125] coupled between the level two cache and the processor in parallel with the level one cache [fig. 1, see streaming engine 125 in parallel with level one cache 123, where both 125 and 123 are between level two cache 130 and processor 110].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, a level one cache coupled to the processor; a level two cache coupled to the level one cache; and a streaming engine coupled between the level two cache and the processor in parallel with the level one cache, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 13, the modified Corbal does not explicitly disclose the method of claim 12, further comprising:
receiving a second instruction, wherein the reverse instruction specifies whether to perform the reverse instruction and the second instruction in parallel; and
determining whether to perform the reverse instruction and the second instruction in parallel based on the reverse instruction.
However, Anderson discloses receiving a second instruction, wherein the reverse instruction specifies whether to perform the reverse instruction and the second instruction in parallel [paragraph 76, “execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bit 0 of the 32-bit wide slot. The p bit determines whether an instruction executes in parallel with a next instruction”]; and
determining whether to perform the reverse instruction and the second instruction in parallel based on the reverse instruction [paragraph 76, “execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bit 0 of the 32-bit wide slot. The p bit determines whether an instruction executes in parallel with a next instruction”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, receiving a second instruction, wherein the reverse instruction specifies whether to perform the reverse instruction and the second instruction in parallel; and determining whether to perform the reverse instruction and the second instruction in parallel based on the reverse instruction, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 14, the modified Corbal does not explicitly disclose the method of claim 12, wherein the reverse instruction specifies a datapath, among multiple data paths, to perform the reverse instruction, the datapath including a functional unit.
However, Anderson wherein the reverse instruction specifies a datapath, among multiple data paths, to perform the reverse instruction, the datapath including a functional unit [fig. 1, datapaths 116, 115; paragraphs 38-39, “Instruction dispatch unit 112 directs each instruction to its target functional unit”, “One part of the dispatch task of instruction dispatch unit 112 is determining whether the instruction is to execute on a functional unit in scalar datapath side A 115 or vector datapath side B 116”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Anderson in the device of the modified Corbal to implement, wherein the reverse instruction specifies a datapath, among multiple data paths, to perform the reverse instruction, the datapath including a functional unit, in order to enable easy decoder alignment, permit more regular layout of instruction fields, and simplify the construction of each decoder which is an advantage for a wide issue VLIW central processor [Anderson, paragraph 75].
Referring to claim 15, the modified Corbal discloses the method of claim 14, wherein the datapath further includes a register file that includes the source register and the destination register [Anderson, paragraph 55, “The two operands are each recalled from an instruction specified register in either global vector register file 231, L2/S2 local register file 232 or predicate register file 234”; “The result may be written into an instruction specified register of global vector register file 231, L2/S2 local register file 222, M2/N2/C local register file 233 or predicate register file 234”].
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Corbal et al (hereinafter Corbal), US 20160179529 A1, in view of Root et al (hereinafter Root), US 6438675 B1, and further in view of Flynn et al (hereinafter Flynn), US 7822955 B2.
Referring to claim 9, Corbal discloses a method comprising:
specifying, by an instruction [paragraph 164, vector bit reversal instruction], a first array and a second array in a memory [paragraph 166, “instruction takes the following form, where DEST is the destination and SRC1 comprises the source”; paragraph 40, “specifies the locations of the source and destination operands, be they in registers or in memory”], in which the first array stores n elements [fig. 20,
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, SRC 2001 storing 8 elements “7” through “0”], wherein n is a positive integer of 4 or greater [in this case, n=8]; and
executing, by processing circuitry, the executing including:
placing the first element of the first array in the nth memory location of the second array [fig. 20, see element “7” placed in 8th lane of DST 2004,
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placing each successive element of the n elements of the first array in a respective preceding memory location of the second array, including placing the nth element of the first array in the first location of second array [see marked up figure 20 above; succeeding element 6 stored in preceding lane 7; succeeding element 5 stored in preceding Ln 6, etc].
Corbal does not explicitly disclose each of the first and second arrays having n contiguous memory locations;
in which a first element of the n elements is stored in a first memory location of the memory locations and each successive element of the n elements is stored in a respective successive memory location of the n memory locations.
However, Root discloses each of the first and second arrays having n contiguous memory locations [col. 1, lines 34-38, “That is, it is presumed that the transfer will be of N data elements from N contiguous locations in the source, starting from the Src address, to N contiguous destination addresses, starting from the Dest address”; Src array and Dest array, both having n contiguous memory locations];
in which a first element of the n elements is stored in a first memory location of the memory locations and each successive element of the n elements is stored in a respective successive memory location of the n memory locations [col 1, lines 34-38, “That is, it is presumed that the transfer will be of N data elements from N contiguous locations in the source, starting from the Src address, to N contiguous destination addresses, starting from the Dest address”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Root in the method of Corbal to implement, each of the first and second arrays having n contiguous memory locations; in which a first element of the n elements is stored in a first memory location of the memory locations and each successive element of the n elements is stored in a respective successive memory location of the n memory locations, in order to provide programming and memory access efficiencies [Root, col. 1, lines 43-44].
The modified Corbal does not explicitly disclose executing, by processing circuitry, the instruction in a single operation.
However, Flynn discloses executing, by processing circuitry, the instruction in a single operation [col. 6, lines 27-30, The first endian reverse instruction is a REV instruction which is arranged to cause the processor core to reverse the order of the bytes in a 32-bit register specified by the REV instruction; col. 7, lines 31-38, “This operation is indicated schematically in FIG. 4B”; “the REV16 instruction is arranged to cause the following operation to be performed:
Rd[31:24]<=Rm[23:16]
Rd[23:16]<=Rm[31:24]
Rd[15:8]<=Rm[7:0]
Rd[7:0]<=Rm[15:8]”; the examiner notes the use of the word “operation” (a single operation)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Flynn in the method of the modified Corbal to implement, executing, by processing circuitry, the instruction in a single operation, in order to efficiently handle data structures other than one predetermined size data word [Flynn, col. 2, lines 27-29].
Referring to claim 10, the modified Corbal discloses the method of claim 9, wherein the instruction specifies a data size of each element of the n elements [Corbal, paragraph 35, “vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes)”].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Corbal, in view of Root, in view of Flynn, as applied to claim 10 above, and further in view of Gonion, US 20150089187 A1.
Referring to claim 11, the modified Corbal does not explicity disclose the method of claim 10, wherein the instruction specifies n.
However, Gonion discloses wherein the instruction specifies n [claim 14, an instruction having a plurality of operands… and wherein the plurality of operands further include a first predicate that includes an attribute… wherein the attribute defines at least one of a size of vector elements in the corresponding vector memory operation, a number of vector elements in the corresponding vector memory operation].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Gonion in the method of the modified Corbal to implement, wherein the instruction specifies n, in order to allow longer vectors thereby speeding up execution without any effort by software developers [Gonion, paragraph 39].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Corbal, in view of Morad, as applied to claim 12 above, and further in view of Gonion, US 20150089187 A1.
Referring to claim 18, the modified Corbal does not explicity disclose the method of claim 12, wherein the reverse instruction specifies n.
However, Gonion discloses wherein the reverse instruction specifies n [claim 14, an instruction having a plurality of operands… and wherein the plurality of operands further include a first predicate that includes an attribute… wherein the attribute defines at least one of a size of vector elements in the corresponding vector memory operation, a number of vector elements in the corresponding vector memory operation].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Gonion in the method of the modified Corbal to implement, wherein the reverse instruction specifies n, in order to allow longer vectors thereby speeding up execution without any effort by software developers [Gonion, paragraph 39].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Gschwind et al, US 20030037221 A1, discloses “a vector instruction identifies a single operation to be performed on a plurality of data elements” [paragraph 16].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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