DETAILED ACTION
Claims 1-20 are pending. This application is a Divisional of 17/660,253 04/22/2022, as Patent 12,299,182. The 17/660,253 claims priority to the Provisional 63/179,681 filed on April 26, 2021.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of U.S. Patent No. 12,229,183. Although the claims at issue are not identical, they are not patentably distinct from each other because they both recite similar features as follows:
Claim 1 Claims 1 & 7 of Patent 12,229,183
A magnetic tunnel junction (MTJ)-based cryptographic engine, comprising:
a sense amplifier; a plurality of MTJs, wherein electrical outputs of the plurality of MTJs are electrically connected to corresponding inputs of the sense amplifier; and a plurality of transistors, wherein the plurality of transistors correspond to electrical inputs of the plurality of MTJs, wherein the MTJ-based cryptographic engine is configured to use variations in the plurality of MTJs to generate a random number,
wherein the plurality of MTJs are configured to be set with same write currents and to provide respective values when the plurality of MTJs are read.
A storage device, comprising:
a magnetic tunnel junction (MTJ)-based storage array, including an array of magnetic tunnel junctions (MTJs);
a magnetic tunnel junction (MTJ)-based cryptographic engine configured to generate a random number based on random variation properties of the MTJs in the MTJ-based storage array, the MTJ-based cryptographic engine including:
a sense amplifier; one or more transistors; and at least two MTJs directly connected to the sense amplifier and the one or more transistors
(claim 7) wherein the MTJs of the
MTJ-based storage array are configured to be set with same write currents and to provide respective values when the
MTJs are read.
Claims 7-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,229,183. Although the claims at issue are not identical, they are not patentably distinct from each other because they both recite similar features as follows:
Claim 7 Claim 1 of Patent 12,229,183
A magnetic tunnel junction (MTJ) device, comprising:
an array of MTJs comprising a plurality of MTJs; a communication interface; and an MTJ-based cryptographic engine configured to generate a random number based on random variation properties of the plurality of MTJs in the array of MTJs, the MTJ-based cryptographic engine including: a sense amplifier; one or more transistors; and at least two MTJs of the plurality of MTJs directly connected to the sense amplifier and the one or more transistors,
wherein the array of MTJs is configured to be damaged by receiving a voltage signal that causes a drop in a resistance of the plurality of MTJs, in response to detection of a tamper event.
A storage device, comprising:
a magnetic tunnel junction (MTJ)-based storage array, including an array of magnetic tunnel junctions (MTJs); a communication interface;
a magnetic tunnel junction (MTJ)-based cryptographic engine configured to generate a random number based on random variation properties of the MTJs in the MTJ-based storage array, the MTJ-based cryptographic engine including:
a sense amplifier; one or more transistors; and at least two MTJs directly connected to the sense amplifier and the one or more transistors
wherein the MTJ-based storage array is configured to be damaged by receiving a voltage signal that causes a drop in a resistance of the MTJs in the MTJ-based
storage array, in response to detection of a tamper event.
Claims 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 12,229,183 in view of Pub 20130073598 (hereinafter Jacobson). Although the claims at issue are not identical, they are not patentably distinct from each other because they both recite similar features as follows:
Claim 14 Claims 1 and 6 of Patent 12,229,183
and Pub 20130073598
setting states of one or more MTJs of an MTJ-based storage array to a same state,
reading respective values from the one or more MTJs; and generating a random number based on the read values.
wherein electrical outputs of the one or more of MTJs are electrically connected to corresponding inputs of a sense amplifier,
wherein one or more transistors correspond to the electrical inputs of the one or more MTJs;
(claim 6) the MTJs of the MTJ-based storage array are configured to be set to a same state and to provide respective values based on a configuration when the MTJs are read.
(claim 1) a magnetic tunnel junction (MTJ)-based cryptographic engine configured to generate a random number based on random variation properties of the MTJs in the MTJ-based storage array,
the MTJ-based cryptographic engine including: a sense amplifier; one or more transistors; and at least two MTJs directly connected to the sense amplifier and the one or more transistors,
(Fig. 5 and related text of Jacobson discloses the connections between the array of MTJs, transistors and a Sense circuit).
Note that Claims 1 and 6 of Patent 12,229,183 does not expressly discloses the connections in detail between the MTJs, the Sense circuit and transistors. Jacobson discloses the transistors connecting to the input sides of the MTJs and the output side of the MTJs connecting to the input side of the sensing circuit (Fig. 5). Therefore, it would have been obvious before the effective filing date of the claimed invention to modify Patent 12,229,183 with Jacobson for the improvement of the generating random values having improved randomness characteristics as discussed in Jacobson.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 12-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub 20130073598 (hereinafter Jacobson)
Regarding claim 1, Jacobson discloses a magnetic tunnel junction (MTJ)-based cryptographic engine, comprising:
a sense amplifier; a plurality of MTJs, wherein electrical outputs of the plurality of MTJs are electrically connected to corresponding inputs of the sense amplifier; and a plurality of transistors, wherein the plurality of transistors correspond to electrical inputs of the plurality of MTJs, wherein the MTJ-based cryptographic engine is configured to use variations in the plurality of MTJs to generate a random number, wherein the plurality of MTJs are configured to be set with same write currents and to provide respective values when the plurality of MTJs are read (Fig. 5 and par. [0051]-[0061] discloses an array of MTJs connecting to transistors and a sensing circuit to generate random values using fixed current or fixed voltage sources).
Regarding claim 2, Jacobson discloses wherein the MTJ-based cryptographic engine is included in a storage device that includes an MTJ-based storage array (Fig. 15 discloses a device comprises the MTJs circuitry as a random number generator).
Regarding claim 3, Jacobson discloses wherein the MTJ-based cryptographic engine is included in a control device electrically connected to a storage device that includes an MTJ-based storage array (Fig. 15, Secure module 1530).
Regarding claim 4, Jacobson discloses wherein the MTJ-based cryptographic engine is configured to be damaged by a shorting voltage based on detection of a tamper event (Fig. 13 and related text discloses the tamper detector using two Ref voltages as comparators for error which should include shorting voltage detection as an indicator of a tamper event).
Regarding claim 5, Jacobson discloses wherein the MTJ-based cryptographic engine is configured to: set states of one or more MTJs of an MTJ-based storage array to a same state; read respective values from the one or more MTJs; and generate a random number based on the read values (Fig. 5 and related text).
Regarding claim 6, Jacobson discloses wherein the MTJ-based cryptographic engine is configured to: set states of one or more MTJs of an MTJ-based storage array using write currents with a same voltage level and a same voltage pulse duration; read respective values from the one or more MTJs; and generate a random number based on the read values (par. [0052]-[0056] discloses the generator can use either current source or voltage source as amplitude of a programming pulse).
Regarding claim 7, Jacobson discloses a magnetic tunnel junction (MTJ) device, comprising:
an array of MTJs comprising a plurality of MTJs; a communication interface; and an MTJ-based cryptographic engine configured to generate a random number based on random variation properties of the plurality of MTJs in the array of MTJs, the MTJ-based cryptographic engine including: a sense amplifier; one or more transistors; and at least two MTJs of the plurality of MTJs directly connected to the sense amplifier and the one or more transistors, wherein the array of MTJs is configured to be damaged by receiving a voltage signal that causes a drop in a resistance of the plurality of MTJs, in response to detection of a tamper event (see claims 1 and 3 rejections. Also, par. [0100] discloses The VREF2 and VREF3 voltages define a target range of resistance values for a MR element under normal operation. Hence, any drop of resistance outside of the normal range (e.g. a short in voltage) indicates a tamper event).
Regarding claim 8, Jacobson discloses wherein the array of MTJs is electrically connected to a control device via the communication interface (Fig. 15 for the Secure Module 1540 (e.g. a control device) comprises the MTJs generator which must include some interface for the Secure Module to obtain the generated random values to send out to the bus 1560).
Regarding claim 12, Jacobson discloses wherein the plurality of MTJs of the array of MTJs are configured to be set to a same state and to provide respective values based on a configuration when the plurality of MTJs are read (claim 5 rejection).
Regarding claim 13, Jacobson discloses wherein the plurality of MTJs of the array of MTJs are configured to be set with same write currents and to provide respective values when the plurality of MTJs are read (claim 6 rejection).
Regarding claims 14-15, the claims are rejected in view of claim 1 rejection.
Regarding claim 16, the claim is rejected in view of claim 6 rejection.
Regarding claim 20, Jacobson discloses wherein the respective values from the one or more MTJs are based on variations in the one or more MTJs (par. [0129] discloses generating random values, a static current may be applied to a MR element having a variable resistance. Hence, in an array of MTJs different resistance value applied to each MR element).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jacobson in view of Pub 20130250662 (hereinafter Katti)
Regarding claim 9, Jacobson discloses wherein the array of MTJs further comprises a tamper detection (Fig. 13) but not expressly disclose a response circuit. Katti discloses in response to detecting tampering a circuitry configured to generate a signal, such as a current or voltage pulse to a MRAM cell rendering the data unretrievable by damaging the MRAM cell. This suggests shorting the circuit (par. [0043]). Therefore, it would have been obvious before the effective filing of the claimed invention to modify Jacobson with Katti to further teach the claimed feature. One would have done so using a tamper protection process in the same field of endeavor with reasonable expectation of success.
Regarding claim 10, the combination of Jacobson and Katti discloses wherein the array of MTJs is electrically connected to a control device comprising a tamper detection and response circuit (see claims 3 and 9 rejections for a control device with the MTJs array random generator comprises built-in a tamper detection and a response circuit).
Regarding claim 11, the combination of Jacobson and Katti discloses wherein the array of MTJs is configured to be damaged by a shorting voltage from a tamper detection (see claim 4 rejection) and response circuit (claim 9 rejection).
Regarding claims 17-18, the claims are rejected in view of claims 10-11 rejections respectively.
Regarding claim 19, the combination of Jacobson and Katti discloses sending a voltage signal to the one or more MTJs in the MTJ-based storage array with a tamper and response circuit that causes a drop in resistance of the one or more MTJs in response to a detection of a tamper event (see claim 9 rejection since shorting a voltage source means creating a very low-resistance).
Inquiry communication
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/TRI M TRAN/Primary Examiner, Art Unit 2432
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