DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8 and 18 are objected to because of the following informalities:
In claim 8, line 5, “application hint” should be “cache storage management hint”.
In claim 18, line 5, “application hint” should be “cache storage management hint”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 7, 9 – 13, 15, 17, and 19 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pandey et al. US Patent Application Publication No. 2025/0156321 (hereinafter referred to as Pandey).
Regarding claim 1, Pandey describes a cache storage managing method, applied to an electronic device comprising a target storage device (system memory 104 (Fig. 1 and page 3, paragraph [0022])) and a cache storage device for storing information which is to be accessed by the target storage device (system level cache (SLC) 122 (Fig. 1 and page 3, paragraph [0022]). System level cache 122 acts as a point of serialization, in that traffic between various SLC clients and system memory 104 passes through system level cache 122 (page 3, paragraph [0028]). The system level cache 122 includes a programmable mapping table 230 and a cache memory 232 (page 4, paragraph [0032]). Memory requests 276 that cannot be satisfied within the cache memory 232 are transmitted via path 280 to the system memory 104 as read operations or write operations (page 4, paragraph [0036])), the cache storage managing method comprising: executing an application installed in the electronic device to generate a cache storage management hint (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220, system power state 254 from the power manager 222, and/or the like (page 4, paragraph [0035]). SLC clients 140 generate memory requests according to the requirements of the application(s) supported by the SLC clients 140. The configurations of a given SLC client 140 and the stream of memory requests generated by the given SLC client 140 are based on one or more applications executed by the SLC client 140… With each memory request, an SLC client 140 generates and transmits a BufferType hint, which encodes information about the memory request pattern for that stream… (page 4, paragraph [0033])); and allocating cache storage space of the cache storage device to at least one sub-device in the electronic device or identifying a priority of a cache portion to be discarded or reserved in the cache storage device (A first technique, referred to as client caching hints, is a hardware-based technique where each SLC client indicates a memory access pattern associated with the SLC client. More specifically, SLC clients indicate a buffer type along with the corresponding memory access request. The buffer type distinguishes different types of buffers used by the SLC clients that can benefit from different cache allocation policies… (page 5, paragraph [0039]). One allocation and replacement control, referred to as cache line allocation, defines where in the LRU chain a particular memory request is allocated. The memory request can allocate in different eviction classes, which can provide isolation and/or protection during victim selection where a victim is a cache line that is selected for eviction (page 5, paragraph [0043]). Another allocation and replacement control, referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like. Further, the promotion technique can vary based on the SLC client that caused the cache line hit. In some embodiments, when CPU 102 causes a cache line hit, the cache line may be promoted to the MRU position, whereas when auxiliary processing subsystem 112 causes a cache line hit, the cache line may be promoted to the LFU position. This approach can be advantageous for use cases where memory accesses by auxiliary processing subsystem 112 are of higher frequency relative to memory accesses by CPU 102 (page 5, paragraph [0044]). Yet another allocation and replacement control, referred to as cache line demotion, demotes a cache line under certain conditions. For example, caching hints from the client can indicate that a current memory request is the last use of the associated memory address by the client. Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045])), according to the cache storage management hint by an operating system of the electronic device (…The cache control parameters 278 determine whether the memory request 276 is allocated at the cache memory 232 and how cache line attributes are set (page 4, paragraph [0036]). …Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045]). Another allocation and replacement control referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like… (page 5, paragraph [0044])).
Regarding claim 2, Pandey describes the cache storage space managing method of claim 1 (see above), wherein the cache storage management hint comprises amount of cache storage space to be allocated to each one of the sub-device (Data received as the initial parameters 350 and runtime updates 352 include: …partition size and/or partition granule size information… percentage of SLC 122 dedicated to each traffic class when multiple traffic classes are active, information regarding which SLC clients 140 are members of each traffic class… (page 7, paragraph [0059])).
Regarding claim 3, Pandey describes the cache storage space managing method of claim 1 (see above), wherein the cache storage management hint comprises conditions of task processing of the application (…When the SLC policy manager 210 determines that the system state has changed, the SLC policy manager 210 transmits updates 262 to the programmable mapping table 230 that are appropriate for the newly determined system state (page 4, paragraph [0035]). …SLC policy manager monitors system state, detects and infers the memory access use case, and dynamically updates the programmable mapping table to optimize the use of the SLC (page 6, paragraph [0051]). SLC policy manager 210 monitors the state of individual SLC clients 140, system activity of computing system 100, and the power state of individual SLC clients 140. Further, SLC policy manager 210 can receive information about the state of the operating system and about the applications executing the various SLC clients 140 (page 6, paragraph [0054])).
Regarding claim 5, Pandey describes the cache storage space managing method of claim 1 (see above), comprising: collecting hardware information of the sub-device, the cache storage device or the target storage device to generate the cache storage management hint, by the application (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220, system power state 254 from the power manager 222, and/or the like (page 4, paragraph [0035]). …The SLC policy manager receives the data for detecting scenarios from the operating system, hardware components, and/or the like. Based on the detected scenario, SLC policy manager updates mappings in the table entries in the PMT to tune the system level cache operation for the detected scenario (page 6, paragraph [0052])).
Regarding claim 7, Pandey describes the cache storage space managing method of claim 1 (see above), wherein an accessing speed of the cache storage device is higher than an accessing speed of the target storage device (In some embodiments, the system memory is implemented with dynamic random access memory (DRAM) devices and/or other similar memory devices. DRAM is a common type of memory that provides a relatively large amount of memory space and low power consumption but with relatively low bandwidth and high access latency relative to other types of memory (page 1, paragraph [0002]). …This type of shared cache is referred to herein as a system level cache SLC) and typically includes a number of cache lines. In some embodiments, the SLC is implemented with static random access memory (SRAM) devices and/or other similar memory devices. SRAM is a common type of memory that provides a relatively small amount of memory space and higher power consumption but with relatively high bandwidth and short access latency relative to other types of memory… (page 1, paragraph [0004])).
Regarding claim 9, Pandey describes the cache storage space managing method of claim 1 (see above), wherein the step of identifying the priority of the cache portion to be discarded or reserved comprises: determining which cache portion of the cache storage device is not used or will not be used to generate a first determination result; increasing the priority of the cache portion to be discarded according to the first determination result (Yet another allocation and replacement control, referred to as cache line demotion, demotes a cache line under certain conditions. For example, caching hints from the client can indicate that a current memory request is the last use of the associated memory address by the client. Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045])).
Regarding claim 10, Pandey describes the cache storage space managing method of claim 1 (see above), wherein the step of identifying the priority of the cache portion to be discarded or reserved comprises: determining a usage frequency of data to generate a second determination result; and increasing the priority of the cache portion to be reserved for the data according to the second determination result (Another allocation and replacement control, referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like. Further, the promotion technique can vary based on the SLC client that caused the cache line hit. In some embodiments, when CPU 102 causes a cache line hit, the cache line may be promoted to the MRU position, whereas when auxiliary processing subsystem 112 causes a cache line hit, the cache line may be promoted to the LFU position. This approach can be advantageous for use cases where memory accesses by auxiliary processing subsystem 112 are of higher frequency relative to memory accesses by CPU 102 (page 5, paragraph [0044])).
Regarding claim 11, Pandey describes an electronic device, comprising: a target storage device (system memory 104 (Fig. 1 and page 3, paragraph [0022])); a cache storage device, which is configured to store information which is to be accessed by the target storage device (system level cache (SLC) 122 (Fig. 1 and page 3, paragraph [0022]). System level cache 122 acts as a point of serialization, in that traffic between various SLC clients and system memory 104 passes through system level cache 122 (page 3, paragraph [0028]). The system level cache 122 includes a programmable mapping table 230 and a cache memory 232 (page 4, paragraph [0032]). Memory requests 276 that cannot be satisfied within the cache memory 232 are transmitted via path 280 to the system memory 104 as read operations or write operations (page 4, paragraph [0036])); and a processing circuit, configured to perform following steps (CPU 102 (Fig. 1 and page 3, paragraph [0022])): executing an application installed in the electronic device to generate cache storage management hint (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220, system power state 254 from the power manager 222, and/or the like (page 4, paragraph [0035]). SLC clients 140 generate memory requests according to the requirements of the application(s) supported by the SLC clients 140. The configurations of a given SLC client 140 and the stream of memory requests generated by the given SLC client 140 are based on one or more applications executed by the SLC client 140… With each memory request, an SLC client 140 generates and transmits a BufferType hint, which encodes information about the memory request pattern for that stream… (page 4, paragraph [0033])); and allocating cache storage space of the cache storage device to at least one sub-device in the electronic device or identifying a priority of a cache portion to be discarded or reserved in the cache storage device (A first technique, referred to as client caching hints, is a hardware-based technique where each SLC client indicates a memory access pattern associated with the SLC client. More specifically, SLC clients indicate a buffer type along with the corresponding memory access request. The buffer type distinguishes different types of buffers used by the SLC clients that can benefit from different cache allocation policies… (page 5, paragraph [0039]). One allocation and replacement control, referred to as cache line allocation, defines where in the LRU chain a particular memory request is allocated. The memory request can allocate in different eviction classes, which can provide isolation and/or protection during victim selection where a victim is a cache line that is selected for eviction (page 5, paragraph [0043]). Another allocation and replacement control, referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like. Further, the promotion technique can vary based on the SLC client that caused the cache line hit. In some embodiments, when CPU 102 causes a cache line hit, the cache line may be promoted to the MRU position, whereas when auxiliary processing subsystem 112 causes a cache line hit, the cache line may be promoted to the LFU position. This approach can be advantageous for use cases where memory accesses by auxiliary processing subsystem 112 are of higher frequency relative to memory accesses by CPU 102 (page 5, paragraph [0044]). Yet another allocation and replacement control, referred to as cache line demotion, demotes a cache line under certain conditions. For example, caching hints from the client can indicate that a current memory request is the last use of the associated memory address by the client. Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045])), according to the cache storage management hint by an operating system of the electronic device (…The cache control parameters 278 determine whether the memory request 276 is allocated at the cache memory 232 and how cache line attributes are set (page 4, paragraph [0036]). …Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045]). Another allocation and replacement control referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like… (page 5, paragraph [0044])).
Regarding claim 12, Pandey describes the electronic device of claim 11 (see above), wherein the cache storage management hint comprises amount of cache storage space to be allocated to each one of the sub-device (Data received as the initial parameters 350 and runtime updates 352 include: …partition size and/or partition granule size information… percentage of SLC 122 dedicated to each traffic class when multiple traffic classes are active, information regarding which SLC clients 140 are members of each traffic class… (page 7, paragraph [0059])).
Regarding claim 13, Pandey describes the electronic device of claim 11 (see above), wherein the cache storage management hint comprises conditions of task processing of the application (…When the SLC policy manager 210 determines that the system state has changed, the SLC policy manager 210 transmits updates 262 to the programmable mapping table 230 that are appropriate for the newly determined system state (page 4, paragraph [0035]). …SLC policy manager monitors system state, detects and infers the memory access use case, and dynamically updates the programmable mapping table to optimize the use of the SLC (page 6, paragraph [0051]). SLC policy manager 210 monitors the state of individual SLC clients 140, system activity of computing system 100, and the power state of individual SLC clients 140. Further, SLC policy manager 210 can receive information about the state of the operating system and about the applications executing the various SLC clients 140 (page 6, paragraph [0054])).
Regarding claim 15, Pandey describes the electronic device of claim 11 (see above), wherein the processing circuit further performs: collecting hardware information of the sub-device, the cache storage device or the target storage device to generate the cache storage management hint, by the application (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220, system power state 254 from the power manager 222, and/or the like (page 4, paragraph [0035]). …The SLC policy manager receives the data for detecting scenarios from the operating system, hardware components, and/or the like. Based on the detected scenario, SLC policy manager updates mappings in the table entries in the PMT to tune the system level cache operation for the detected scenario (page 6, paragraph [0052])).
Regarding claim 17, Pandey describes the electronic device of claim 11 (see above), wherein an accessing speed of the cache storage device is higher than an accessing speed of the target storage device (In some embodiments, the system memory is implemented with dynamic random access memory (DRAM) devices and/or other similar memory devices. DRAM is a common type of memory that provides a relatively large amount of memory space and low power consumption but with relatively low bandwidth and high access latency relative to other types of memory (page 1, paragraph [0002]). …This type of shared cache is referred to herein as a system level cache SLC) and typically includes a number of cache lines. In some embodiments, the SLC is implemented with static random access memory (SRAM) devices and/or other similar memory devices. SRAM is a common type of memory that provides a relatively small amount of memory space and higher power consumption but with relatively high bandwidth and short access latency relative to other types of memory… (page 1, paragraph [0004])).
Regarding claim 19, Pandey describes the electronic device of claim 11 (see above), wherein the step of identifying the priority of the cache portion to be discarded or reserved comprises: determining which cache portion of the cache storage device is not used or will not be used to generate a first determination result; increasing the priority of the cache portion to be discarded according to the first determination result (Yet another allocation and replacement control, referred to as cache line demotion, demotes a cache line under certain conditions. For example, caching hints from the client can indicate that a current memory request is the last use of the associated memory address by the client. Such a caching hint can indicate that the corresponding cache line is no longer needed and, therefore, can be evicted from the cache memory (page 6, paragraph [0045])).
Regarding claim 20, Pandey describes the electronic device of claim 11 (see above), wherein the step of identifying the priority of the cache portion to be discarded or reserved comprises: determining a usage frequency of data to generate a second determination result; and increasing the priority of the cache portion to be reserved for the data according to the second determination result (Another allocation and replacement control, referred to as cache line promotion, promotes a cache line when the cache line is hit. The hit cache line can get promoted to the MRU position, to the next level position in the LRU chain, to the LFU position, and/or the like. Further, the promotion technique can vary based on the SLC client that caused the cache line hit. In some embodiments, when CPU 102 causes a cache line hit, the cache line may be promoted to the MRU position, whereas when auxiliary processing subsystem 112 causes a cache line hit, the cache line may be promoted to the LFU position. This approach can be advantageous for use cases where memory accesses by auxiliary processing subsystem 112 are of higher frequency relative to memory accesses by CPU 102 (page 5, paragraph [0044])).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 6, 8, 14, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey in view of Hughes et al. US Patent No. 9158702 (herein after referred to as Hughes).
Regarding claim 4, Pandey describes the cache storage space managing method of claim 1 (see above), comprising: using a first allocation policy to allocate the cache storage space before receiving the cache storage management hint; generating a second allocation policy according to the cache storage management hint after receiving the cache storage management hint, by the operating system; and using the second allocation policy to allocate the cache storage space (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220… (page 4, paragraph [0035]). At initial startup, SLC 122 is fully shared by the SLC clients 140 via path 384. Policy holder module 310 can modify the initial startup configuration by receiving initial parameters 350, parsing and categorizing the initial parameters 350, and storing the resulting configuration data 354 in SLC configuration 314. SLC configuration 314 transmits the configuration data to relevant components of SLC policy manger 210. In that regard, SLC configuration 314 transmits broadcast updates 356 to generic event handler module 316, broadcast updates 358 to event rate debounce module 318, and broadcast updates 360 and 362 to partition manager module 320. The components of SLC policy manger 210 begin execution using the configuration data in the SLC configuration 314 (page 7, paragraph [0057]). Over time, policy holder module 310 can modify the current configuration by receiving runtime updates 352, parsing and categorizing the runtime updates 352, and storing the resulting updated configuration data in SLC configuration 314. SLC configuration 314 transmits the updated configuration data to relevant components of SLC policy manager 210. In that regard, SLC configuration 314 transmits broadcast updates 356 to generic event handler module 316, broadcast updates 358 to event rate debounce module 318, and broadcast updates 360 and 362 to partition manager module 320. The components of SLC policy manager 210 continue execution using the updated configuration data in SLC configuration 314 (page 7, paragraph [0058])). Pandey does not explicitly disclose that the allocations are done by the operating system.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that the OS may be capable of handling page replacement priority, allocation/deallocation/eviction.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of page replacement [allocation] by OS as taught by Hughes in the Pandey system because the operating system is clearly capable of handling memory space allocation and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 6, Pandey describes the cache storage space managing method of claim 1 (see above), comprising: collecting hardware information of the sub-device, the cache storage device or the target storage device by the operating system; and allocating the cache storage space according to the hardware information and the cache storage management hint (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220… (page 4, paragraph [0035]). …The SLC policy manager receives the data for detecting scenarios from the operating system, hardware components, and/or the like. Based on the detected scenario, SLC policy manager updates mappings in the table entries in the PMT to tune the system level cache operation for the detected scenario (page 6, paragraph [0052]). …SLC policy manager monitors system state, detects and infers the memory access use case, and dynamically updates the programmable mapping table to optimize the use of the SLC (page 6, paragraph [0051])). Pandey does not explicitly disclose that the allocations are done by the operating system.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that the OS may be capable of handling page replacement priority, allocation/deallocation/eviction.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of page replacement [allocation] by OS as taught by Hughes in the Pandey system because the operating system is clearly capable of handling memory space allocation and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 8, Pandey describes the cache storage space managing method of claim 1 (see above). Pandey does not specifically disclose further comprising: providing an API (application programming interface) to the application by the operating system, thereby the application can transmit the application hint to the operating system to control allocation of the cache storage device.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that a hint may be passed via API.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of hint passing via API as taught by Hughes in the Pandey system because the APIs are conventional computer system communication and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 14, Pandey describes the electronic device of claim 11 (see above), wherein the processing circuit further performs: using a first allocation policy to allocate the cache storage space before receiving the cache storage management hint; generating a second allocation policy according to the cache storage management hint after receiving the cache storage management hint, by the operating system; and using the second allocation policy to allocate the cache storage space (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220… (page 4, paragraph [0035]). At initial startup, SLC 122 is fully shared by the SLC clients 140 via path 384. Policy holder module 310 can modify the initial startup configuration by receiving initial parameters 350, parsing and categorizing the initial parameters 350, and storing the resulting configuration data 354 in SLC configuration 314. SLC configuration 314 transmits the configuration data to relevant components of SLC policy manger 210. In that regard, SLC configuration 314 transmits broadcast updates 356 to generic event handler module 316, broadcast updates 358 to event rate debounce module 318, and broadcast updates 360 and 362 to partition manager module 320. The components of SLC policy manger 210 begin execution using the configuration data in the SLC configuration 314 (page 7, paragraph [0057]). Over time, policy holder module 310 can modify the current configuration by receiving runtime updates 352, parsing and categorizing the runtime updates 352, and storing the resulting updated configuration data in SLC configuration 314. SLC configuration 314 transmits the updated configuration data to relevant components of SLC policy manager 210. In that regard, SLC configuration 314 transmits broadcast updates 356 to generic event handler module 316, broadcast updates 358 to event rate debounce module 318, and broadcast updates 360 and 362 to partition manager module 320. The components of SLC policy manager 210 continue execution using the updated configuration data in SLC configuration 314 (page 7, paragraph [0058])). Pandey does not explicitly disclose that the allocations are done by the operating system.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that the OS may be capable of handling page replacement priority, allocation/deallocation/eviction.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of page replacement [allocation] by OS as taught by Hughes in the Pandey system because the operating system is clearly capable of handling memory space allocation and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 16, Pandey describes the electronic device of claim 11 (see above), wherein the processing circuit further performs: collecting hardware information of the sub-device, the cache storage device or the target storage device by the operating system; and allocating the cache storage space according to the hardware information and the cache storage management hint (Concurrently, the SLC policy manager 210 executes as a background process, receiving use case data 252 from the operating system 220… (page 4, paragraph [0035]). …The SLC policy manager receives the data for detecting scenarios from the operating system, hardware components, and/or the like. Based on the detected scenario, SLC policy manager updates mappings in the table entries in the PMT to tune the system level cache operation for the detected scenario (page 6, paragraph [0052]). …SLC policy manager monitors system state, detects and infers the memory access use case, and dynamically updates the programmable mapping table to optimize the use of the SLC (page 6, paragraph [0051])). Pandey does not explicitly disclose that the allocations are done by the operating system.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that the OS may be capable of handling page replacement priority, allocation/deallocation/eviction.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of page replacement [allocation] by OS as taught by Hughes in the Pandey system because the operating system is clearly capable of handling memory space allocation and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 18, Pandey describes the electronic device of claim 11 (see above). Pandey does not specifically disclose wherein the processing circuit further performs: providing an API (application programming interface) to the application by the operating system, thereby the application can transmit the application hint to the operating system to control allocation of the cache storage device.
Hughes discloses implementing a scratchpad memory within a cache using priority hints. Specifically, it describes that to determine the actual per-page replacement priority, one embodiment of the OS 902 includes replacement priority logic 903 which combines the hint 904 conveyed through the user API 901 with other metrics 914 which may be determined from the processor/core microarchitecture 913, such as hardware performance counters and monitoring schemes. Such metrics allow replacement priority logic 903 to keep track of shared cache usage, and to adjust the priority for each page to enable fair sharing (column 10, lines 38 – 50). Hughes makes clear that a hint may be passed via API.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Hughes teachings in the Pandey system. Skilled artisan would have been motivated to incorporate the method of hint passing via API as taught by Hughes in the Pandey system because the APIs are conventional computer system communication and would be obvious to try. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache memory replacement management. This close relation between both of the references highly suggests an expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tan et al. US Patent Application Publication No. 2013/0031298 describes a composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics. The system includes performance-related hints in requests. Mola US Patent Application Publication No. 2024/0095187 describes a system for logging cache line lifetime hints.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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June 27, 2026
Prosecution Insights