Prosecution Insights
Last updated: October 26, 2026
Application No. 19/180,211

COMPARATOR, ANALOG TO DIGITAL CONVERTER, AND OFFSET CANCELLATION METHOD THEREOF

Non-Final OA §102
Filed
Apr 16, 2025
Priority
May 07, 2024 — TW 113116904
Examiner
JEANGLAUDE, JEAN BRUNER
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1111 granted / 1186 resolved
+25.7% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 7m
Avg Prosecution
24 currently pending
Career history
1207
Total Applications
across all art units

Statute-Specific Performance

§101
8.4%
-31.6% vs TC avg
§103
29.6%
-10.4% vs TC avg
§102
35.8%
-4.2% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1186 resolved cases

Office Action

§102
Detailed Office Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 7, 10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Huang (USPGPUB 2022/0337261). Regarding claims 1, 10, Huang disclose a comparator and method (fig. 1) , comprising: a comparator circuit configured to generate a decision signal according to an input signal; an offset calculation circuit configured to calculate an offset of the comparator circuit according to the decision signal to generate a plurality of control signals (paragraphs 0015 – 0018; 0026 – 0029, 0033); a hybrid offset voltage generation circuit configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the control signals and utilize the first reference voltage and the second reference voltage to perform a charge transfer operation to generate a plurality of calibration voltages (paragraphs 0015 – 0018); and an offset cancellation circuit configured to cancel the offset according to the plurality of calibration voltages (0021). PNG media_image1.png 527 810 media_image1.png Greyscale Regarding claim 7, Huang disclose an analog-to-digital converter (fig. 3) , comprising: a plurality of comparator circuits (COM1, COM2, fig. 3) configured to generate a plurality of decision signals according to an input signal; an offset calculation circuit configured to calculate an offset of the plurality of comparator circuits according to the plurality of decision signals to generate a plurality sets of control signals (figs. 3, 4); a hybrid offset voltage generation circuit configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the plurality of sets of control signals and utilize the first reference voltage and the second reference voltage to perform a charge transfer operation to generate a plurality sets of calibration voltages (figs. 3, 4; paragraphs 0027 – 0032); and a plurality of offset cancellation circuits configured to cancel the offset according to the plurality sets of calibration voltages (paragraph 0029) . PNG media_image2.png 515 714 media_image2.png Greyscale Allowable Subject Matter Claims 2 – 6, 8, 9, 11 – 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEAN B JEANGLAUDE/ Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Apr 16, 2025
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+5.6%)
1y 7m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1186 resolved cases by this examiner. Grant probability derived from career allowance rate.

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