Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in Instant Application.
Priority
Examiner acknowledges Applicant’s claim to priority benefits of U.S Patent 11438414 filed 05/28/2019.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/29/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered if signed and initialed by the Examiner.
Double Patenting
A rejection based on double patenting of the "same invention" type finds its support in the language of 35 U.S.C. 101 which states that "whoever invents or discovers any new and useful process ... may obtain a patent therefor ..." (Emphasis added). Thus, the term "same invention," in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957); and In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the conflicting claims so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-16, 18-20 of U.S. Patent No. 12301659. Although the claims at issue are not identical, they are not patentably distinct from each other.
U.S. Patent 12301659
Instant Application
1, 13, 16. A device, comprising: a first memory; and a processor configured to: execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; map a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory in the apparatus separate from the device; wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory; wherein the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus.
1. A device, comprising: a first memory; and a processor configured to: execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; map a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory.
4. The device of claim 1, wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory.
2, 14. The device of claim 1, wherein the processor is further configured to: allocate a first page of the virtual memory to an application; map the first page to a second page in the second memory on the apparatus; migrate content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory; and remap the first page of the virtual memory to the third page in the first memory on the device.
2. The device of claim 1, wherein the processor is further configured to: allocate a first page of the virtual memory to an application; map the first page to a second page in the second memory on the apparatus; migrate content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory; and remap the first page of the virtual memory to the third page in the first memory on the device.
3, 15. The device of claim 2, wherein the processor is further configured to: migrate content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time; and remap the first page of the virtual memory to the second page in the second memory on the apparatus.
3. The device of claim 2, wherein the processor is further configured to: migrate content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time; and remap the first page of the virtual memory to the second page in the second memory on the apparatus.
5, 18. The device of claim 4, wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: allocate a third page in the first memory of the device; store the content, retrieved from the second page in the second memory on the apparatus, in the third page in the first memory; generate a page table entry mapping the first page of the virtual memory to the third page in the first memory; store the page table entry in the page tables in the first memory; and load the page table entry into the translation lookaside buffer to resolve the page fault.
5. The device of claim 4, wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus; allocate a third page in the first memory of the device; store the content, retrieved from the second page in the second memory on the apparatus, in the third page in the first memory; generate a page table entry mapping the first page of the virtual memory to the third page in the first memory; store the page table entry in the page tables in the first memory; and load the page table entry into the translation lookaside buffer to resolve the page fault.
6. The device of claim 5, wherein the processor is further configured to: deallocate the second page after the page table entry is stored in the page tables in the first memory.
6. The device of claim 5, wherein the processor is further configured to: deallocate the second page after the page table entry is stored in the page tables in the first memory.
7. The device of claim 5, wherein the processor is further configured to: return the second page borrowed from the apparatus after the page table entry is stored in the page tables in the first memory.
7. The device of claim 5, wherein the processor is further configured to: return the second page borrowed from the apparatus after the page table entry is stored in the page tables in the first memory.
8, 19. The device of claim 5, wherein the processor is further configured to: transmit current content of the first page of the virtual memory stored in the third page in the first memory of the device to the second page in the second memory one the apparatus; and update the page table entry to map the first page of the virtual memory to the second page in the second memory on the apparatus.
8, 19. The device of claim 5, wherein the processor is further configured to: transmit current content of the first page of the virtual memory stored in the third page in the first memory of the device to the second page in the second memory one the apparatus; and update the page table entry to map the first page of the virtual memory to the second page in the second memory on the apparatus.
9, 20. The device of claim 5, wherein the processor is further configured to: allocate a fourth page in the second memory on the apparatus; transmit current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and update the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus.
9, 20. The device of claim 5, wherein the processor is further configured to: allocate a fourth page in the second memory on the apparatus; transmit current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and update the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus.
10. The device of claim 4, wherein the microprocessor and the first memory are configured in a same computer chip.
10. The device of claim 4, wherein the microprocessor and the first memory are configured in a same computer chip.
11. The device of claim 1, wherein a portion of the first operating system running in the device is virtualized for execution in the lender device via the second operating system running in the apparatus.
11. The device of claim 1, wherein a portion of the first operating system running in the device is virtualized for execution in the lender device via the second operating system running in the apparatus.
12. The device of claim 1, wherein the first operating system running in the device is configured to amount the second memory as a virtual memory device to make available the second memory to applications running in the device.
12. The device of claim 1, wherein the first operating system running in the device is configured to amount the second memory as a virtual memory device to make available the second memory to applications running in the device.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 11438414. Although the claims at issue are not identical, they are not patentably distinct from each other.
U.S. Patent 11438414
Instant Application
1. A device, comprising: a first memory; and a processor configured to: execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; map a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory in the apparatus separate from the device; wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory; wherein the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus.
1, 13, 16. A device, comprising: a first memory; and a processor configured to: execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; map a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory.
4, 17. The device of claim 1, wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory.
2. The computing device of claim 1, further configured as the borrower device to: allocate a first page of the virtual memory to an application; map the first page to a second page in the amount of memory on the lender device; migrate content of the second page from the amount of memory on the lender device to third page in the local memory of the borrower device in response to the application executed in the microprocessor using the first page of the virtual memory; remap the first page of the virtual memory to the third page in the local memory of the borrower device.
2, 14. The device of claim 1, wherein the processor is further configured to: allocate a first page of the virtual memory to an application; map the first page to a second page in the second memory on the apparatus; migrate content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory; and remap the first page of the virtual memory to the third page in the first memory on the device.
3. The computing device of claim 2, further configured as the borrower device to: migrate content of the third page in the local memory of the borrower device to the second page of the amount of memory on the lender device, after the first page of the virtual page has not been used for a period of time; and remap the first page of the virtual memory to the second page of the amount of memory on the lender device.
3, 15. The device of claim 2, wherein the processor is further configured to: migrate content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time; and remap the first page of the virtual memory to the second page in the second memory on the apparatus.
4. The computing device of claim 1, wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; in response to the translation lookaside buffer or at least one microprocessor identifying a page fault in accessing a first page of the virtual memory, the borrower device is further configured to: retrieve content of the first page of the virtual memory stored in a second page in the amount of memory on the lender device by running the first operating system to communicate with the second operating system running in the lender device; allocate a third page in the local memory of the borrower device; store the content, retrieved from the second page on the lender device, in the third page in the local memory; generate a page table entry mapping the first page of the virtual memory to the third page in the local memory; store the page table entry in the page tables in the local memory; and load the page table entry into the translation lookaside buffer to resolve the page fault.
5, 18. The device of claim 4, wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory: retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus; allocate a third page in the first memory of the device; store the content, retrieved from the second page in the second memory on the apparatus, in the third page in the first memory; generate a page table entry mapping the first page of the virtual memory to the third page in the first memory; store the page table entry in the page tables in the first memory; and load the page table entry into the translation lookaside buffer to resolve the page fault.
5. The computing device of claim 4, further configured as the borrower device to: deallocate the second page.
6. The device of claim 5, wherein the processor is further configured to: deallocate the second page after the page table entry is stored in the page tables in the first memory.
6. The computing device of claim 4, further configured as the borrower device to: return the second page borrowed from the lender device.
7. The device of claim 5, wherein the processor is further configured to: return the second page borrowed from the apparatus after the page table entry is stored in the page tables in the first memory.
7. The computing device of claim 4, further configured as the borrower device to: transmit current content of the first page of the virtual memory stored in the third page in the local memory of the borrower device to the second page in the amount of memory on the lender device; and update the page table entry to map the first page of the virtual memory to the second page in the amount of memory on the lender device.
8, 19. The device of claim 5, wherein the processor is further configured to: transmit current content of the first page of the virtual memory stored in the third page in the first memory of the device to the second page in the second memory one the apparatus; and update the page table entry to map the first page of the virtual memory to the second page in the second memory on the apparatus.
8. The computing device of claim 4, further configured as the borrower device to: allocate a fourth page in the amount of memory on the lender device; transmit current content of the first page of the virtual memory stored in the third page in the local memory to the fourth page in the amount of memory on the lender device; and update the page table entry to map the first page of the virtual memory to the fourth page in the amount of memory on the lender device.
9, 20. The device of claim 5, wherein the processor is further configured to: allocate a fourth page in the second memory on the apparatus; transmit current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and update the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus.
9. The computing device of claim 1, wherein the microprocessor and the local memory are configured in a same computer chip; the borrower device is further configured to lend memory to at least one further borrower device; and the lender device is further configured to borrow memory from at least one further lender device.
10. The device of claim 4, wherein the microprocessor and the first memory are configured in a same computer chip.
10. The computing device of claim 1, wherein a portion of the first operating system running in the borrower device is virtualized for execution in the lender device via the second operating system running in the lender device.
11. The device of claim 1, wherein a portion of the first operating system running in the device is virtualized for execution in the lender device via the second operating system running in the apparatus.
11. The computing device of claim 1, wherein the lender device offers the amount of memory on the lender device as a virtual memory device; and the first operating system running in the computing device configured as the borrower device is further configured to make available the virtual memory device in the borrower device to expand the memory capacity of the borrower device.
12. The device of claim 1, wherein the first operating system running in the device is configured to amount the second memory as a virtual memory device to make available the second memory to applications running in the device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Harper et al., “hereinafter Harper” (U.S. Patent Application Publication: 20140280669) in view of Hepkin et al., “hereinafter Hepkin” (U.S. Patent Application Publication: 20120102258).
As per Claim 1, Harper discloses a device, comprising: a first memory (Harper, Para.17, Memory can be shared among computing devices that are communicationally coupled to one another, such as via a network.); and a processor configured to:
execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses (Harper, Para.17, An operating system can provide, to locally executing applications, a locally addressable memory namespace that include capacity that is actually supported by the physical memory of one or more remote computing devices. Such operating system mechanisms can also adjust the amount of memory available for sharing among multiple computing devices, Para.30, the portion 116 that is being shared, a page fault can be generated, and virtual memory mechanisms can be utilized to move some other data from other portions of the memory 115 to disk, thereby making room to swap back into the memory 115 the data that was previously swapped out to disk.);
communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system (Harper, Para.9, operating systems of individual computing devices sharing memory can comprise functionality to adjust the amount of storage of such memory that is shared, as well as functionality to map, into the process space of processes executing on such computing devices, storage capacity supported by memory that is remote from the computing device on which such processes are executing., Para.30, the portion 116 that is being shared, a page fault can be generated, and virtual memory mechanisms can be utilized to move some other data from other portions of the memory 115 to disk, thereby making room to swap back into the memory 115 the data that was previously swapped out to disk.);
map a first portion of the virtual memory addresses to physical memory addresses of address the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of second memory in the apparatus separate from the device (Harper, Para.5, memory that is physically part of one computing device can be mapped into the process space, of and be directly accessible by, processes executing on another, different computing device that is communicationally coupled to the first computing device. The locally addressable memory namespace of one computing device is, thereby, supported by memory that can physically be on another, different computing device, Para.36, the processes executing on the computing device 130, such as the exemplary job 140, can directly address the larger locally addressable memory namespace 231 and can have portions thereof mapped into the process space of those processes. Such a larger locally addressable memory namespace 231 can be supported by, not only the memory 135 that is installed on the server computing device 130, but can also by remote memory, such as the memory 125, which is physically installed on another, different computing device. The processes executing on the computing device 130, however, can be agnostic as to what physical memory is actually represented by the locally addressable memory namespace 231);
However Harper does not explicitly discloses virtual memory addresses and borrow the second memory.
Hepkin discloses virtual memory addresses (Hepkin, Para.53, The hypervisor receives a page fault with a virtual address from the virtual machine, as indicated at block 501. The hypervisor determines, at decision block 503, if the page is designated affinitized. If not, the hypervisor returns a physical address mapping to the processor, at block 509, and instructs the processor's memory management unit to restart the request, at block 511.) and borrow the second memory (Hepkin, Para.53, the hypervisor to borrow some extra memory on the destination computer system).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Harper with the teachings as in Hepkin. The motivation for doing so would have been for dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system. Embodiments of the method migrate processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. (Hepkin, Para.12).
With respect to Claim 13 and Claim 16 are substantially similar to Claim 1 and are rejected in the same manner, the same art and reasoning applying.
As per Claim 2, Harper in view of Hepkin disclose the device of claim 1, wherein the processor is further configured to:
allocate a first page of the virtual memory to an application; map the first page to a second page in the second memory on the apparatus; (Harper, Para.24, a memory page table, or other like memory interface mechanism can identify specific portions of the locally addressable memory namespace, such as specific pages, or specific address ranges, that can be associated with the remote memory interface 131. A LOAD or STORE instruction, or other like instruction, directed to those portions of the locally addressable memory namespace can be directed to the remote memory interface 131. Thus, the locally addressable memory namespace, as utilizable by the processes being executed by the server computing device 130, can be greater than the physical memory 135 because the remote memory interface 131 can utilize the memory of remote computing devices, such as, for example, the memory 125 of the server computing device 120, or the memory 115 of the server computing device 110, to support an increased memory namespace on the computing device 130.);
migrate content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory (Harper, Para.21, virtual memory mechanisms are utilized, whereby some data is "swapped" from the memory to slower non-volatile storage media, such as a hard disk drive. In such a manner, more memory capacity is made available. When the data that was swapped from the memory to the disk is attempted to be read from the memory by an executing process, a page fault can be generated, and processing can be temporarily suspended while such data is read back from the slower disk and again stored in the memory, from which it can then be provided to the processing units. As will be recognized by those skilled in the art, such a process can introduce delays that can be undesirable, especially in a server computing context.); and remap the first page of the virtual memory to the third page in the first memory on the device (Harper, Para.09, operating systems of individual computing devices sharing memory can comprise functionality to adjust the amount of storage of such memory that is shared, as well as functionality to map, into the process space of processes executing on such computing devices, storage capacity supported by memory that is remote from the computing device on which such processes are executing).
With respect to Claim 14 is substantially similar to Claim 2 and is rejected in the same manner, the same art and reasoning applying.
As per Claim 3, Harper in view of Hepkin disclose the device of claim 2, wherein the processor is further configured to:
migrate content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time (Harper, Para.21, virtual memory mechanisms are utilized, whereby some data is "swapped" from the memory to slower non-volatile storage media, such as a hard disk drive. In such a manner, more memory capacity is made available. When the data that was swapped from the memory to the disk is attempted to be read from the memory by an executing process, a page fault can be generated, and processing can be temporarily suspended while such data is read back from the slower disk and again stored in the memory, from which it can then be provided to the processing units. As will be recognized by those skilled in the art, such a process can introduce delays that can be undesirable, especially in a server computing context, Para.31, the memory sharing controller 170 may only be able to adjust the amount of memory being shared by any specific computing device during defined periods of time such as, for example, while that computing device is restarting, or during periods of time when that computing device has suspended the execution of other tasks.); and remap the first page of the virtual memory to the second page in the second memory on the apparatus (Harper, Para.09, operating systems of individual computing devices sharing memory can comprise functionality to adjust the amount of storage of such memory that is shared, as well as functionality to map, into the process space of processes executing on such computing devices, storage capacity supported by memory that is remote from the computing device on which such processes are executing).
With respect to Claim 15 is substantially similar to Claim 3 and is rejected in the same manner, the same art and reasoning applying.
As per Claim 4, Harper in view of Hepkin disclose the device of claim 1, wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory (Hepkin, Para.30, an effective address (EA), such as the instruction fetch address within IFAR 333, is the address of data or an instruction generated by a processor. The EA specifies a segment register and offset information within the segment. To access data (including instructions) in memory, the EA is converted to a real address (RA), through one or more levels of translation, associated with the physical location where the data or instructions are stored.).
The same motivation that was utilized for combining Harper in view of Hepkin as set forth in claim 1 is equally applicable to claim 4.
With respect to Claim 17 is substantially similar to Claim 4 and is rejected in the same manner, the same art and reasoning applying.
As per Claim 9, Harper in view of Hepkin disclose the device of claim 5, wherein the processor is further configured to: allocate a fourth page in the second memory on the apparatus; transmit current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and update the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus (Harper, Para.30, The memory sharing controller 170 can then, as an example, request that the server computing device 110 increase the portion 116 of the memory 115 that it has made available for sharing. In response, in one embodiment, the operating system or other like control mechanisms, executing on the server computing device 110, can swap data stored in those portions of the memory 115 that were previously assigned to processes executing locally on the server computing device 110, and store such data on, for example, a hard disk drive… virtual memory mechanisms can be utilized to move some other data from other portions of the memory 115 to disk, thereby making room to swap back into the memory 115 the data that was previously swapped out to disk, Para.28, specific pages of memory, specific addresses of memory, or other like identifiers can be utilized to delineate the locally addressable memory namespace from the memory storage capacity that is reserved for utilization by a remote memory interface, and is, thereby, shared with processes executing on remote computing devices. Thus, for example, the locally addressable memory namespace that can be utilized by processes executing on the server computing device 120 can be supported by the portion of the memory 125 that excludes the portion 126 that is set aside for sharing. In a similar manner, the locally addressable memory namespace that can be utilized by processes executing on the server computing device 110 can be supported by the portion of the memory 115 that excludes the portion 116.).
With respect to Claim 20 is substantially similar to Claim 9 and is rejected in the same manner, the same art and reasoning applying.
As per Claim 10, Harper in view of Hepkin disclose the device of claim 4, wherein the microprocessor and the first memory are configured in a same computer chip (Harper, Para.53, the system memory 430 and other components of the computing device 400 can be physically co-located, such as on a single chip. In such a case, some or all of the system bus 421 can be nothing more than communicational pathways within a single chip structure and its illustration in FIG. 4 can be nothing more than notational convenience for the purpose of illustration.).
As per Claim 11, Harper in view of Hepkin disclose the device of claim 1, wherein a portion of the first operating system running in the device is virtualized for execution in the lender device via the second operating system running in the apparatus (Harper, Para.30, the memory sharing controller 170 can continually adjust the amount of memory storage capacity being shared. In such an embodiment, the operating systems, or other like control mechanisms, of individual computing devices can comprise mechanisms by which the size of the locally addressable memory namespace can be dynamically altered during runtime. For example, execution of the job 140, by the server computing device 130, can result in an increased demand for memory. In response, processes executing on the server computing device 130 can communicate with the memory sharing controller 170 and can request additional shared memory. The memory sharing controller 170 can then, as an example, request that the server computing device 110 increase the portion 116 of the memory 115 that it has made available for sharing.).
As per Claim 12, Harper in view of Hepkin disclose the device of claim 1, wherein the first operating system running in the device is configured to amount the second memory as a virtual memory device to make available the second memory to applications running in the device (Harper, Para.17, An operating system can provide, to locally executing applications, a locally addressable memory namespace that include capacity that is actually supported by the physical memory of one or more remote computing devices. Such operating system mechanisms can also adjust the amount of memory available for sharing among multiple computing devices, Para.28, the amount of memory storage capacity that is made available for sharing can be coordinated by a centralized mechanism, such as the memory sharing controller 170. For example, the memory sharing controller 170 can receive information from computing devices, such as the exemplary server computing devices 110, 120 and 130, and can decide, based upon such received information, an amount of memory storage capacity of the server computing devices 110, 120 and 130 that is to be made available for sharing.).
As per Claim 13, Harper discloses a method, comprising: (Harper, Para.17, Memory can be shared among computing devices that are communicationally coupled to one another, such as via a network.); and a processor configured to:
executing, by a processor of a device having a first memory, instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses (Harper, Para.17, An operating system can provide, to locally executing applications, a locally addressable memory namespace that include capacity that is actually supported by the physical memory of one or more remote computing devices. Such operating system mechanisms can also adjust the amount of memory available for sharing among multiple computing devices.);
communicating, by the device, with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system (Harper, Para.9, operating systems of individual computing devices sharing memory can comprise functionality to adjust the amount of storage of such memory that is shared, as well as functionality to map, into the process space of processes executing on such computing devices, storage capacity supported by memory that is remote from the computing device on which such processes are executing. );
mapping, by the processor, a first portion of the virtual memory addresses to physical memory addresses configured to address the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses configured to address the second memory in the apparatus separate from the device (Harper, Para.5, memory that is physically part of one computing device can be mapped into the process space, of and be directly accessible by, processes executing on another, different computing device that is communicationally coupled to the first computing device. The locally addressable memory namespace of one computing device is, thereby, supported by memory that can physically be on another, different computing device, Para.36, the processes executing on the computing device 130, such as the exemplary job 140, can directly address the larger locally addressable memory namespace 231 and can have portions thereof mapped into the process space of those processes. Such a larger locally addressable memory namespace 231 can be supported by, not only the memory 135 that is installed on the server computing device 130, but can also by remote memory, such as the memory 125, which is physically installed on another, different computing device. The processes executing on the computing device 130, however, can be agnostic as to what physical memory is actually represented by the locally addressable memory namespace 231);
However Harper does not explicitly discloses virtual memory addresses and borrow the second memory.
Hepkin discloses virtual memory addresses (Hepkin, Para.53, The hypervisor receives a page fault with a virtual address from the virtual machine, as indicated at block 501. The hypervisor determines, at decision block 503, if the page is designated affinitized. If not, the hypervisor returns a physical address mapping to the processor, at block 509, and instructs the processor's memory management unit to restart the request, at block 511.) and borrow the second memory (Hepkin, Para.53, the hypervisor to borrow some extra memory on the destination computer system).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Harper with the teachings as in Hepkin. The motivation for doing so would have been for dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system. Embodiments of the method migrate processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. (Hepkin, Para.12).
With respect to Claim 16 is substantially similar to Claim 13 and are rejected in the same manner, the same art and reasoning applying.
Allowable Subject Matter
Claim 5-9 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Schmisseur et al. (US 20190042122) teaches TECHNOLOGIES FOR EFFICIENTLY MANAGING ALLOCATION OF MEMORY IN A SHARED MEMORY POOL.
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/NORMIN ABEDIN/Primary Examiner, Art Unit 2449
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