DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on April 17, 2025 and October 28, 2025 were filed on/after the filing date of the application on April 17, 2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on April 17, 2025. These drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 11-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 4-10, and 12-20 of U.S. Patent No. 12,299,768. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #19/181,443
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11
U.S. Patent #12,299,768
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14
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8
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10
Present Application #19/181,443
12
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U.S. Patent #12,299,768
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Present Application #19/181,443 Claim 1
U.S. Patent #12,299,768 Claim 1
A graphics processing unit comprising a plurality of cores,
A graphics processing unit comprising a plurality of cores,
wherein each core of the plurality of cores comprises a slave unit configured to manage the execution of image rendering tasks within the core, and
wherein each core of the plurality of cores comprises a slave unit configured to manage the execution of image rendering tasks within the core, and
wherein at least one of the plurality of cores further comprises a master unit configured to:
wherein at least one of the plurality of cores further comprises a master unit configured to:
receive a set of image rendering tasks;
receive a set of image rendering tasks;
assign a first subset of the image rendering tasks to a first core of the plurality of cores;
assign a first subset of the image rendering tasks to a first core of the plurality of cores;
assign a second subset of the image rendering tasks to a second core of the plurality of cores;
assign a second subset of the image rendering tasks to a second core of the plurality of cores;
transmit the first subset of the image rendering tasks to the slave unit of the first core; and
transmit the first subset of the image rendering tasks to the slave unit of the first core; and
transmit the second subset of the image rendering tasks to the slave unit of the second core.
transmit the second subset of the image rendering tasks to the slave unit of the second core;
wherein: the slave unit of the first core is configured to transmit to the master unit a first credit notification when a task in the first subset of the image rendering tasks has been processed, the slave unit of the second core is configured to transmit to the master unit a second credit notification when a task in the second subset of the image rendering tasks has been processed; and
the master unit is configured to: store a credit number for each of the first and second cores, adjust the credit number of the first core by a first amount for each task in the first subset of the image rendering tasks when the master unit assigns the first subset of the image rendering tasks to the first core,
adjust the credit number of the second core by the first amount for each task in the second subset of the image rendering tasks when the master unit assigns the second subset of the image rendering tasks to the second core,
adjust the credit number of the first core by a second amount when the master unit receives the first credit notification, and
adjust the credit number of the second core by the second amount when the master unit receives the second credit notification, wherein one of the first and second amounts is positive, and the other is negative.
Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
NOTE: Claim 1 of the present application is similar in scope to claim 11 of the present application, thus may be rejected under similar rationale as claim of the present application.
Present Application #19/181,443 Claim 2
U.S. Patent #12,299,768 Claim 4
The graphics processing unit of claim 1, wherein:
The graphics processing unit of claim 1, wherein:
the first subset of the image rendering tasks comprises a first task, wherein the first task is a task on which a dependent task depends;
the first subset of the image rendering tasks comprises a first task, wherein the first task is a task on which a dependent task depends;
the master unit is configured to include, in the first subset of the image rendering tasks and following the first task, a task completion update command;
the master unit is configured to include, in the first subset of the image rendering tasks and following the first task, a task completion update command;
the slave unit of the first core is configured to send a first task completion update to the master unit when the first core processes the task completion update command;
the slave unit of the first core is configured to send a first task completion update to the master unit when the first core processes the task completion update command;
the master unit is configured to assign and transmit a dependent task of the first task to one of the slave units of the first and second cores only after the master unit has received the first task completion update; and
the master unit is configured to assign and transmit a dependent task of the first task to one of the slave units of the first and second cores only after the master unit has received the first task completion update; and
the dependent task of the first task is a task that depends on the results of the first task.
the dependent task of the first task is a task that depends on the results of the first task.
Present Application #19/181,443 Claim 3
U.S. Patent #12,299,768 Claim 14
The graphics processing unit of claim 2, wherein
The method of claim 13, further comprising:
the master unit is configured to include with the first subset of the image rendering tasks, following the first task and optionally before the task completion update command, a memory flush command,
including, by the master unit, after the first task in the first subset of the image rendering tasks and optionally before the task completion update command, a memory flush command;
wherein the slave unit of the first core is configured to write all processed work stored in the first core to a shared memory when the first core processes the memory flush command.
processing, by the first core, the memory flush command; and writing, by the slave unit of the first core, all output data stored in the first core to a shared memory.
Present Application #19/181,443 Claim 4
U.S. Patent #12,299,768 Claim 5
The graphics processing unit of claim 1, wherein each core in the plurality of cores comprises a second slave unit configured to manage the execution of a second type of image rendering task by the core, and wherein one of the cores comprises a second master unit configured to:
The graphics processing unit of claim 1, wherein each core in the plurality of cores comprises a second slave unit configured to manage the execution of a second type of image rendering task by the core, and wherein one of the cores comprises a second master unit configured to:
receive a second set of image rendering tasks of the second type;
receive a second set of image rendering tasks of the second type;
assign a first subset of the second set of image rendering tasks to a first one of the plurality of cores;
assign a first subset of the second set of image rendering tasks to a first one of the plurality of cores;
assign a second subset of the second set of image rendering tasks to a second, different one of the plurality of cores;
assign a second subset of the second set of image rendering tasks to a second, different one of the plurality of cores;
transmit the first subset of the second set of image rendering tasks to the second slave unit of the first one of the plurality of cores; and
transmit the first subset of the second set of image rendering tasks to the second slave unit of the first one of the plurality of cores; and
transmit the second subset of the second set of image rendering tasks to the second slave unit of the second one of the plurality of cores.
transmit the second subset of the second set of image rendering tasks to the second slave unit of the second one of the plurality of cores.
Present Application #19/181,443 Claim 5
U.S. Patent #12,299,768 Claim 6
The graphics processing unit of claim 1, wherein:
The graphics processing unit of claim 1, wherein:
the master unit is configured to output first and second register write commands;
the master unit is configured to output first and second register write commands;
the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and
the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and
the plurality of cores are connected by a register bus configured to communicate register write commands between the cores.
the plurality of cores are connected by a register bus configured to communicate register write commands between the cores.
Present Application #19/181,443 Claim 6
U.S. Patent #12,299,768 Claim 7
The graphics processing unit of claim 5, wherein at least the core comprising the master unit further comprises an arbiter unit in communication with the master unit and the slave unit of the core, wherein the arbiter unit is configured to:
The graphics processing unit of claim 6, wherein at least the core comprising the master unit further comprises an arbiter unit in communication with the master unit and the slave unit of the core, wherein the arbiter unit is configured to:
receive the register write commands from the master unit; and
receive the register write commands from the master unit; and
for each register write command:
for each register write command:
if the register write command is addressed to the core comprising the master unit, pass the register write command to the slave unit of the core comprising the master unit, and
if the register write command is addressed to the core comprising the master unit, pass the register write command to the slave unit of the core comprising the master unit; and
if the register write command is not addressed to the core comprising the master unit, forward the register write command for transmission over the register bus.
if the register write command is not addressed to the core comprising the master unit, forward the register write command for transmission over the register bus.
Present Application #19/181,443 Claim 7
U.S. Patent #12,299,768 Claim 8
The graphics processing unit of claim 5, wherein the plurality of cores each comprise an interface unit in communication with the register bus, wherein the interface unit of the core comprising the master unit is configured to:
The graphics processing unit of claim 6, wherein the plurality of cores each comprise an interface unit in communication with the register bus, wherein the interface unit of the core comprising the master unit is configured to:
receive the first and second register write commands; and
receive the first and second register write commands; and
transmit, over the register bus, the first register write command to the first core and the second register write command to the second core;
transmit, over the register bus, the first register write command to the first core and the second register write command to the second core;
wherein the interface unit of the first core is configured to:
wherein the interface unit of the first core is configured to:
receive, via the register bus, the first register write command, and forward the first register write command to the slave unit of the first core; and
receive, via the register bus, the first register write command, and forward the first register write command to the slave unit of the first core; and
wherein the interface unit of the second core is configured to:
wherein the interface unit of the second core is configured to:
receive, via the register bus, the second register write command, and forward the second register write command to the slave unit of the second core.
receive, via the register bus, the second register write command, and forward the second register write command to the slave unit of the second core.
Present Application #19/181,443 Claim 8
U.S. Patent #12,299,768 Claim 9
The graphics processing unit of claim 7, wherein the interface unit of the first core is configured to:
The graphics processing unit of claim 8, wherein the interface unit of the first core is configured to:
determine whether the first register write command is addressed to a first reserved register address; and
determine whether the first register write command is addressed to a first reserved register address; and
if the first register write command is addressed to the first reserved register address, forward the first register write command to the slave unit of the first core, and wherein the interface unit of the second core is configured to:
if the first register write command is addressed to the first reserved register address, forward the first register write command to the slave unit of the first core, and wherein the interface unit of the second core is configured to:
determine whether the second register write command is addressed to a second reserved register address, and
determine whether the second register write command is addressed to a second reserved register address; and
if the second register write command is addressed to the second reserved register address, forward the second register write command to the slave unit of the second core.
if the second register write command is addressed to the second reserved register address, forward the second register write command to the slave unit of the second core.
Present Application #19/181,443 Claim 11
U.S. Patent #12,299,768 Claim 10
A method of transmitting image rendering tasks in a graphics processing unit comprising a plurality of cores, the method comprising:
A method of transmitting image rendering tasks in a graphics processing unit comprising a plurality of cores, the method comprising:
receiving, by a master unit in a core of the plurality of cores, a set of image rendering tasks;
receiving, by a master unit in a core of the plurality of cores, a set of image rendering tasks;
assigning, by the master unit, a first subset of the image rendering tasks to a first core of the plurality of cores;
assigning, by the master unit, a first subset of the image rendering tasks to a first core of the plurality of cores;
assigning, by the master unit, a second subset of the image rendering tasks to a second core of the plurality of cores;
assigning, by the master unit, a second subset of the image rendering tasks to a second core of the plurality of cores;
transmitting, by the master unit, the first subset of image rendering tasks to a slave unit of the first core; and
transmitting, by the master unit, the first subset of image rendering tasks to a slave unit of the first core;
transmitting, by the master unit, the second subset of image rendering tasks to a slave unit of the second core.
transmitting, by the master unit, the second subset of image rendering tasks to a slave unit of the second core;
storing, by the master unit, a credit number for each of the first and second cores;
adjusting, by the master unit, the credit number of the first core by a first amount for each task in the first subset of the image rendering tasks; and
adjusting, by the master unit, the credit number of the second core by the first amount for each task in the second subset of image rendering tasks;
transmitting, by the slave unit of the first core to the master unit, a first credit notification when a task in the first subset of image rendering tasks has been processed;
transmitting, by the slave unit of the second core to the master unit, a second credit notification when a task in the second subset of image rendering tasks has been processed;
adjusting, by the master unit, the credit number of the first core by a second amount when the master unit receives the first credit notification; and
adjusting, by the master unit, the credit number of the second core by the second amount when the master unit receives the second credit notification, wherein one of the first and second amounts is positive, and the other is negative.
Claim 11 of the present application differs from claim 10 of the patent application in that claim 11 of the present application is broader in scope than claim 10 of the patent application, thus encompasses that of the patent application.
Present Application #19/181,443 Claim 12
U.S. Patent #12,299,768 Claim 12
The method of claim 11, further comprising:
The method of claim 10, further comprising:
assigning image rendering tasks to the first and second cores in direct relation to a first number of available processing units (PUs), and to a second number of available PUs,
assigning image rendering tasks to the first and second cores in direct relation to a first number of available processing units (PUs), and to a second number of available PUs,
wherein the first number of available PUs is the number of available PUs in the first core and the second number of available PUs is the number of available PUs in the second core.
wherein the first number of available PUs is the number of available PUs in the first core and the second number of available PUs is the number of available PUs in the second core.
Present Application #19/181,443 Claim 13
U.S. Patent #12,299,768 Claim 13
The method of claim 11, wherein the method further comprises:
The method of claim 10, wherein the method comprises:
including, by the master unit, after a first task in the first subset of the image rendering tasks, a task completion update command;
including, by the master unit, after a first task in the first subset of the image rendering tasks, a task completion update command;
processing, by the first core, the first task;
processing, by the first core, the first task;
processing, by the first core, the task completion update command; and
processing, by the first core, the task completion update command; and
transmitting, by the slave unit of the first core, a task completion update to the master unit;
transmitting, by the slave unit of the first core, a task completion update to the master unit;
assigning, by the master unit, a dependent task of the first task to one of the slave units of the first and second cores; and
assigning, by the master unit, a dependent task of the first task to one of the slave units of the first and second cores; and
transmitting, by the master unit, the dependent task to the core to which it has been assigned.
transmitting, by the master unit, the dependent task to the core to which it has been assigned.
Present Application #19/181,443 Claim 14
U.S. Patent #12,299,768 Claim 14
The method of claim 13, further comprising:
The method of claim 13, further comprising:
including, by the master unit, after the first task in the first subset of the image rendering tasks and optionally before the task completion update command, a memory flush command;
including, by the master unit, after the first task in the first subset of the image rendering tasks and optionally before the task completion update command, a memory flush command;
processing, by the first core, the memory flush command; and
processing, by the first core, the memory flush command; and
writing, by the slave unit of the first core, all output data stored in the first core to a shared memory.
writing, by the slave unit of the first core, all output data stored in the first core to a shared memory.
Present Application #19/181,443 Claim 15
U.S. Patent #12,299,768 Claim 15
The method of claim 11, further comprising:
The method of claim 10, further comprising:
receiving, by a second master unit in any one of the plurality of cores, a second set of image rendering tasks of a second type;
receiving, by a second master unit in any one of the plurality of cores, a second set of image rendering tasks of a second type;
assigning, by the second master unit, a first subset of the second set of image rendering tasks to the first core;
assigning, by the second master unit, a first subset of the second set of image rendering tasks to the first core;
assigning, by the second master unit, a second subset of the second set of image rendering tasks to the second core;
assigning, by the second master unit, a second subset of the second set of image rendering tasks to the second core;
transmitting, by the second master unit, the first subset of the second set of image rendering tasks to a second slave unit of the first core; and
transmitting, by the second master unit, the first subset of the second set of image rendering tasks to a second slave unit of the first core; and
transmitting, by the second master unit, the second subset of the second set of image rendering tasks to a second slave unit of the second core.
transmitting, by the second master unit, the second subset of the second set of image rendering tasks to a second slave unit of the second core.
Present Application #19/181,443 Claim 16
U.S. Patent #12,299,768 Claim 16
The method of claim 11, wherein:
The method of claim 10, wherein:
the transmitting of the first and second subsets comprises outputting by the master unit, first and second register write commands;
the transmitting of the first and second subsets comprises outputting, by the master unit, first and second register write commands;
the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and
the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and
the plurality of cores are connected by a register bus for communicating the register write commands between the cores.
the plurality of cores are connected by a register bus for communicating the register write commands between the cores.
Present Application #19/181,443 Claim 17
U.S. Patent #12,299,768 Claim 17
A method of manufacturing a graphics processing unit as set forth in claim 1, comprising inputting an integrated circuit definition dataset of said graphics processing unit into an integrated circuit manufacturing system, causing said integrated circuit manufacturing system to manufacture said graphics processing unit.
A method of manufacturing a graphics processing unit as set forth in claim 1, the method comprising inputting to an integrated circuit manufacturing system an integrated circuit definition dataset that, when processed in said integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture said graphics processing unit.
Present Application #19/181,443 Claim 18
U.S. Patent #12,299,768 Claim 18
A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 11 to be performed when the code is run on at least one processor.
A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 10 to be performed when the code is run.
Present Application #19/181,443 Claim 19
U.S. Patent #12,299,768 Claim 19
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing unit as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing unit.
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing unit as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing unit.
Present Application #19/181,443 Claim 20
U.S. Patent #12,299,768 Claim 20
An integrated circuit manufacturing system configured to manufacture a graphics processing unit as set forth in claim 1.
An integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing unit as set forth in claim 1;
a layout processing system configured to process the computer readable dataset description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing unit; and
an integrated circuit generation system configured to manufacture the graphics processing unit according to the circuit layout description.
Claim 20 of the present application differs from claim 20 of the patent application in that claim 20 of the present application is broader in scope than claim 20 of the patent application, thus encompasses that of the patent application.
Allowable Subject Matter
Claims 1-20 would be allowable if the Double Patenting rejection set forth above may be overcome.
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The present inveiton relates to a graphics processing unit (GPU) comprising a plurality of cores and managing distribution and execution of image rendering tasks amongst the plurality of cores.
Prior art includes:
Champigny (US 2021/0294648) discloses a graphics processing unit (Figure 1, graphics processing unit (GPU) 120 of computing system 100) comprising a plurality of cores (e.g. GPU cores 132), wherein each core of the plurality of cores comprises a slave (e.g. as secondary GPU cores 132), and wherein at least one of the plurality of cores further comprises a master (e.g. as primary GPU core 132)([0029] notes one of GPU cores may be assigned primary status, referred to as a “primary GPU core” and all remaining GPU cores 132 may be assigned a secondary status, referred to as “secondary GPU cores”)(Figure 6B) configured to: receive a set of image rendering tasks (e.g. step 614, [0041] notes retrieving a task from the task register of shared memory section); assign a first subset of the image rendering tasks to a first core of the plurality of cores (e.g. assign task portion of task to one of secondary GPU core); assign a second subset of the image rendering tasks to a second core of the plurality of cores (e.g. assign task portion of task to a different one of secondary GPU core)(step 616, [0041] notes dividing the task into task portions, e.g. subtasks, and step 618, [0041] notes assigning each of the task portions to a different GPU core, e.g. one or more of secondary GPU cores 132 as well as itself, e.g. primary GPU core 132); transmit the first subset of the image rendering tasks to the first core (e.g. transmit task portion of task to the one of secondary GPU core); and transmit the second subset of the image rendering tasks to the second core (e.g. transmit task portion of task to the different one of secondary GPU core)(e.g. step 618, [0041] notes assigning each of the task portions to a different GPU core, step 620, [0041] notes causing execution of the task portions by the secondary GPU cores and step 622, [0041] notes executing own task portion, thus denoting task portions “transmitted” to GPU cores such that may be executed as described);
Price et al. (US 2017/0236244)(cited in the Information Disclosure Statement (IDS) filed April 17, 2025) disclose a plurality of cores (Figure 1, GPUs 5, 6, further illustrated in Figure 2 and further illustrated as GPUs 60, 61, 62, 63 of Figure 6, where [0194] notes GPUs 5, 6, as shader core GPUs), wherein each core of the plurality of cores comprises a slave unit configured to manage the execution of image rendering tasks within the core (job manager (JM) of GPUs configured as slave), and wherein at least one of the plurality of cores further comprises a master unit (job manager (JM) of GPUs configured as master) configured to: receive a set of image rendering tasks (e.g. receive graphics processing tasks); assign a first subset of the image rendering tasks to a first core of the plurality of cores; assign a second subset of the image rendering tasks to a second core of the plurality of cores (e.g. partitions the graphics processing tasks as subtasks for each of the plurality of GPUs); transmit the first subset of the image rendering tasks to the first core; and transmit the second subset of the image rendering tasks to the second core (e.g. transmit the subtasks to each of the plurality of GPUs)([0206] notes driver 4 conveys graphics processing tasks to job manager of the master GPU, then job manager partitions the graphics processing tasks into subtasks and distributes the subtasks to the different GPUs); and
Al-Kadi et al. (US 8,607,246) further disclose a plurality of cores (Figure 1), wherein each core of the plurality of cores comprises a slave (e.g. slave cores 12), and wherein at least one of the plurality of cores further comprises a master unit (e.g. master core 10 with hardware task scheduler 14) configured to: receive a set of image rendering tasks (Figure 2, set of tasks 20, where column 2, lines 55-57 notes master core 10 executes a program of instructions that include instructions to initiate execution of a set of tasks by slave cores 12); assign a first subset of the image rendering tasks to a first core of the plurality of cores; assign a second subset of the image rendering tasks to a second core of the plurality of cores (column 2, lines 62 thru column 3, lines 3, lines 56 thru column 4, lines 5 notes the instructions to initiate execution of the set of tasks cause master core 10 to send signals to hardware task scheduler 14, the instruction identifying the tasks in the set, a repetitive pattern between the tasks for a class of positions in the set and optionally a boundary dependency pattern for a further class in the set and/or parameters of the tasks); transmit the first subset of the image rendering tasks to the first core; and transmit the second subset of the image rendering tasks to the second core (column 4, lines 4-46 notes upon reception of task identification, slave cores 12 may load the program(s) of instructions for executing the identified task).
Although the prior art cited above discloses certain features of the claimed invention as outlined above, the prior art of record fails to teach or suggest, singly or combined, the limitations of independent claims 1, 11, and 17-20 as recited as a whole, more specifically, “…wherein each core of the plurality of cores comprises a slave unit configured to manage the execution of image rendering tasks within the core, and wherein at least one of the plurality of cores further comprises a master unit configured to… transmit the first subset of the image rendering tasks to the slave unit of the first core; and transmit the second subset of the image rendering tasks to the slave unit of the second core…” as recited.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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