DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 08/31/2026 have been fully considered but they are not persuasive.
Applicant argues that the combination of Singh et al. (“Singh”) and Zainuddin et al. (“Zainuddin”) fails to teach or suggest: “receiving, by the memory sub-system from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command.”
Applicant characterizes Singh as being limited to discovery of exposed storage devices using token values and characterizes Zainuddin as being limited to determining ramp rates for NAND word lines. Applicant therefore contends that neither reference teaches the claimed host-to-memory-sub-system access command containing a sub-block descriptor.
The Examiner respectfully disagrees.
The rejection is based on the combined teachings of Singh and Zainuddin, rather than on either reference individually. Singh provides the underlying host/storage-device environment in which a host communicates commands and information to a storage system and in which vendor-specific information may be used to characterize or select storage-device functionality. As set forth in the previous Office Action, Singh discloses a discovery controller receiving a discovery command from a host system, including vendor-specific discovery mechanisms and parameters associated with storage-device configurations.
Zainuddin is relied upon for its additional teaching that a memory device may perform operations at a granularity smaller than a larger memory structure. In particular, Zainuddin ¶0096 describes embodiments permitting “sub-block level operations” by selectively accessing word lines relative to a joint. Thus, Zainuddin demonstrates that access to a memory structure need not necessarily be performed only at the granularity of the entire larger memory structure. The fact that Zainuddin implements its sub-block operations at the NAND-memory level does not, by itself, negate the relevance of its teaching concerning selective access to less than the entirety of a larger memory structure.
Applicant's argument appears to address the references separately and to require Zainuddin itself to disclose the complete host-command architecture recited by claim 1. Such a showing is not required for an obviousness rejection. The relevant inquiry is what the collective teachings of the prior art would have suggested to one of ordinary skill in the art.
In view of Singh's teaching of host-issued commands and vendor-specific information for communicating storage-device capabilities, together with Zainuddin's teaching that memory operations may be performed at a sub-block granularity, it would have been obvious to one of ordinary skill in the art to provide information associated with a host access command identifying the sub-block or portion upon which the requested operation is to be performed. Such identification would permit the memory sub-system to determine which portion of the addressed storage structure is the intended target of the requested sub-block operation, rather than requiring operation on the entire addressed structure.
Applicant further argues that Zainuddin is directed specifically to determining RC characteristics and ramp rates for word lines during NAND programming. This characterization of Zainuddin is acknowledged; however, it does not render its disclosure of sub-block operations irrelevant. A reference is considered for all that it reasonably teaches to one of ordinary skill in the art, and the rejection does not require bodily incorporation of Zainuddin's particular ramp-rate implementation into Singh. Rather, Zainuddin is relied upon for the broader technical teaching that operations within a memory device may selectively address a sub-block portion of a larger memory structure.
Accordingly, Applicant's argument that neither Singh nor Zainuddin individually discloses the entire claimed arrangement does not overcome the rejection based upon their combined teachings. The rejection of claims 1, 10, and 19 under 35 U.S.C. §103 is therefore maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh et al. [US 2025/0306800 A1] in view of Zainuddin et al. [US 2024/0071493 A1].
Claim 1 is rejected over Singh and Zainuddin.
Singh teaches “A method, comprising: configuring, by a memory sub-system, a vendor specific log page to indicate that the memory sub-system supports sub block access and to specify a sub block granularity level for the sub block access;” as “In some configurations, feature discovery request 532.2 may be based on a vendor-specific discovery log page generated based on a group identifier included in a vendor specific parameter in the discovery command.” [¶0059]
“receiving, by the memory sub-system from a host system, a command to get the vendor specific log page;” as “The discovery controller may receive a discovery command from a host system that includes a token value, where the token values map to different storage device configurations among the exposed storage devices.” [Abstract]
“providing, by the memory sub-system, the vendor specific log page; and” as “ a storage node may include data storage devices of a variety of capacities, port configurations, vendors, input/output capabilities, etc.” [¶0048]
Singh does not explicitly teach receiving, by the memory sub-system from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command.
However, Zainuddin teaches “receiving, by the memory sub-system from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command.” as “in some embodiments, allow for sub-block level operations by accessing word lines only above or below the joint.” [¶0096]
Singh and Zainuddin are analogous arts because they teach data storage system and accessing on sub-blocks.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Singh and Zainuddin before him/her, to modify the teachings of Singh to include the teachings of Zainuddin with the motivation of the amount of ramp rate reduction used for the fastest word lines can be selected to balance the amount of Icc peak reduction against its effect on programming performance. [Zainuddin, ¶0151]
Claim 10 is rejected over Singh and Zainuddin under the same rationale of rejection of claim 1.
Claim 19 is rejected over Singh and Zainuddin under the same rationale of rejection of claim 1.
Allowable Subject Matter
Claims 2, 11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The applied prior art of Singh et al. US 2025/0306800 A1 and Zainuddin et al. US 2024/0071493 A1 fails to teach or suggest “transferring, by the memory sub-system according to an opcode provided in the access command and between the memory sub-system and the host system, data for the portion of the logical block without transferring between the memory sub-system and the host system data of the logical block outside of the portion of the logical block identified by the sub block descriptor,” as presently claimed in claims 2, 11 and 20.
In particular, Singh et al. generally teaches storage access operations and command handling for memory devices, but does not disclose or suggest selectively transferring only a specified portion of a logical block based on a sub block descriptor while avoiding transfer of remaining data outside the identified portion. Singh et al. instead operates on conventional block-level data transfers in which the entire addressed logical block is transferred between the host and the memory sub-system.
Likewise, Zainuddin et al. discloses techniques associated with storage management and data access granularity, but fails to teach or suggest an opcode-directed partial logical block transfer mechanism in which only the data corresponding to the sub block descriptor is transferred between the host system and the memory sub-system, while data outside the identified portion of the logical block is intentionally not transferred.
Accordingly, the combination of Singh et al. and Zainuddin et al. would not have rendered obvious the claimed selective sub-block transfer operation that reduces unnecessary host-memory data movement by transferring only a designated portion of a logical block according to the opcode and sub block descriptor.
Claims 3-9 and 12-18 are objected being dependent on already object claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
