DETAILED ACTION
The current Office Action is in response to the papers submitted 04/17/2025. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kantani et al. (Pub. No.: US 2024/0094932) referred to as Kantani.
Regarding claim 1, Kantani teaches a memory device [2, Fig 1]; and
a memory controller [3, Fig 1] coupled to the memory device [2, Fig 1] and configured to:
receive a first write request [S1, S11, S12, and S13, Fig 12; A write that gets written in SLC is considered a first write request], wherein the first write request [S1, S11, S12, and S13, Fig 12] comprises a first type of data [S12 and S13; Data written to SLC is system data type of data]; and
label a first data tag for the first type of data in response to the first write request [S13, Fig 12; Fig 14; Paragraph 0038; Writing to SLC tags the system data with physical address information indicating the data is in SLC memory for later retrieval using the conversion table], wherein the first data tag indicates that the first type of data is stored in a first type of memory cell [SLC AREA, Fig 9; S13, Fig 12] of the memory device [2, Fig 1].
Regarding claim 2, Kantani teaches the first write request [S1, S11, S12, and S13, Fig 12] comprises a first identification bit, the first identification bit is marked as a first value, the first value represents a first request format corresponding to the first write request, and the first request format is a format set for the first type of data [IDENTIFICATION FLAG, Fig 10; Paragraphs 0076 – 0077; The identification flag is a bit that indicates if the data to be written is either system data or not system data].
Regarding claim 3, Kantani teaches the memory controller [3, Fig 1] is further configured to label the first data tag for the first type of data based on the first value of the first identification bit [IDENTIFICATION FLAG, Fig 10; S13, Fig 12; Fig 14; Paragraphs 0038 and 0076 - 0077; The physical address assigned to data is based on the identification flag].
Regarding claim 4, Kantani teaches the memory controller [3, Fig 1] is further configured to:
receive a second write request, wherein the second write request comprises a second type of data [S1, S11, S12, and S14; Paragraph 0080; A write to the QLC area shows the data is of a second type that is not system data]; and
write the second type of data into the first type of memory cell or a second type of memory cell [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080] in the memory device [2, Fig 1] in response to the second write request [S1, S11, S12, and S14; Paragraph 0080], wherein the first type of memory cell [SLC AREA, Fig 9; S13, Fig 12] is configured to be capable of being written with N-bit data, the second type of memory cell is configured to be capable of being written with M-bit data, and N is less than M [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080; SLC writes 1 bit of data per cell where QLC writes more then one bit of memory per cell].
Regarding claim 5, Kantani teaches the first type of data comprises system file data of an operating system [S12 and S13; Data written to SLC is system data type of data], and the second type of data comprises data other than the system file data [S1, S11, S12, and S14; Paragraph 0080; A write to the QLC area shows the data is of a second type that is not system data].
Regarding claim 6, Kantani teaches wherein a second value of the first identification bit in the second write request is different from the first value [IDENTIFICATION FLAG, Fig 10; Paragraphs 0076 – 0077; A “1” indicates system data and a “0” indicates user data that is not system data].
Regarding claim 7, Kantani teaches the memory controller [3, Fig 1] is further configured to send the first type of data labeled with the first data tag to the memory device [S13, Fig 12]; and
the memory device [2, Fig 1] is configured to write the first type of data labeled with the first data tag into the first type of memory cell [Fig 9; S13, Fig 12; The controller sends a write data labeled with a physical address of the SLC to the SLC area of the memory where the memory processed to store the data].
Regarding claim 8, Kantani teaches the memory controller [1, Fig 1] is further configured to send a write instruction to the memory device [2, Fig 1; S13, Fig 12], wherein the write instruction comprises the first type of data labeled with the first data tag and a first memory address corresponding to the first type of data [S13, Fig 12; Fig 14; The controller write instruction to the SLC area along with a tag memory address indicating where to store the system data in the SLC area]; and
the memory device [2, Fig 1] is further configured to:
receive the write instruction [S13, Fig 12]; and
in response to the write instruction, write the first type of data labeled with the first data tag in the first type of memory cell based on the first memory address [S13, Fig 12; The memory device 2 receives the write instruction from the controller 3 and writes the system data into a physical area of the SLC area based on the physical address tag assigned to the system data by the controller 3].
Regarding claim 9, Kantani teaches the memory controller [3, Fig 1] is further configured to control the first type of data to perform data migrate between the first type of memory cell based on the first data tag [S18 and S19; Fig 13; Paragraph 0089; When garbage collection is performed in the SLC area on system data the system data is moved from one SLC cell block to another SLC cell block].
Regarding claim 10, Kantani teaches the memory controller [3, Fig 1] is further configured to:
receive a read request for requesting to read the first type of data; and
in response to the read request, send a read instruction to the memory device, wherein the read instruction comprises an address of a first type of memory cell for storing the first type of data; and
the memory device [2, Fig 1] is configured to:
receive the read instruction; and
in response to the read instruction, read the first type of data from the first type of memory cell [S16, Fig 13; Fig 14; Paragraphs 0033, 0037, 0041, and 0048; Data that is written into the SLC area is later read from the SLC area due to a read request from the host which would include the address of where to read the data from].
Regarding claim 11, Lee teaches the memory device [2, Fig 1] comprises the first type of memory cell [SLC AREA, Fig 9] and a second type of memory cell [QLC AREA, Fig 9];
the first type of memory cell comprises at least one of a Single-Level Cell (SLC) [SLC AREA, Fig 9], a Multi- Level Cell (MLC), or a Trinary-Level Cell (TLC); and
the second type of memory cell comprises a Quad-Level Cell (QLC) [QLC AREA, Fig 9].
Regarding claim 12, Kantani teaches an interface [Fig 1; The line showing a data connection between host 4 and controller 3 shows there is an interface on host that the connection connects to]; and
a processor [4a, Fig 1] coupled to the interface [Fig 1; The line showing a data connection between host 4 and controller 3 shows there is an interface on host that the connection connects to] and configured to:
send a first write request [S1, S11, S12, and S13, Fig 12; A write that gets written in SLC is considered a first write request] to a memory controller [3, Fig 1] through the interface [Fig 1; The line showing a data connection between host 4 and controller 3 shows there is an interface on host that the connection connects to], wherein the first write request [S1, S11, S12, and S13, Fig 12] comprises a first type of data [S12 and S13; Data written to SLC is system data type of data], the first write request [S1, S11, S12, and S13, Fig 12] indicates the memory controller [3, Fig 1] to label a first data tag for the first type of data [S13, Fig 12; Fig 14; Paragraph 0038; Writing to SLC tags the system data with physical address information indicating the data is in SLC memory for later retrieval using the conversion table], and the first data tag indicates that the first type of data is stored in a first type of memory cell [SLC AREA, Fig 9; S13, Fig 12] of a memory device [2, Fig 1].
Regarding claim 13, Kantani teaches the processor [4a, Fig 1] is further configured to send a second write request to the memory controller [3, Fig 1] through the interface [Fig 1; The line showing a data connection between host 4 and controller 3 shows there is an interface on host that the connection connects to], wherein the second write request comprises a second type of data [S1, S11, S12, and S14; Paragraph 0080; A write to the QLC area shows the data is of a second type that is not system data], and the second write request [S1, S11, S12, and S14; Paragraph 0080] indicates to write the second type of data to the first type of memory cell or a second type of memory cell [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080] of the memory device [2, Fig 1], wherein the first type of memory cell is configured to be capable of being written with N-bit data, the second type of memory cell is configured to be capable of being written with M-bit data, and N is less than M [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080; SLC writes 1 bit of data per cell where QLC writes more then one bit of memory per cell].
Regarding claim 14, Kantani teaches the first write request [S1, S11, S12, and S13, Fig 12] comprises a first identification bit, the first identification bit is marked as a first value, the first value represents a first request format corresponding to the first write request, and the first request format is a format set for the first type of data [IDENTIFICATION FLAG, Fig 10; Paragraphs 0076 – 0077; The identification flag is a bit that indicates if the data to be written is either system data or not system data]; and
a second value of the first identification bit in the second write request is different from the first value [IDENTIFICATION FLAG, Fig 10; Paragraphs 0076 – 0077; A “1” indicates system data and a “0” indicates user data that is not system data].
Regarding claim 15, Kantani teaches the processor [4a, Fig 1] runs an operating system [Paragraphs 0031 and 0051; The CPU of a personal computer runs the operating system of the personal computer];
the first type of data comprises system file data of the operating system [S12 and S13; Data written to SLC is system data type of data of the operating system]; and
the processor [4a, Fig 1] is further configured to:
automatically generate the first write request during an installation of the operating system; or
after the operating system is installed, receive a write operation for the operating system, generate the first write request in response to the write operation [Paragraph 0038; The write request to the controller comes from the host which shows the write request is received after the operating system on the host is installed in response to a write operation on the host].
Regarding claim 16, Kantani teaches the processor [4a, Fig 1] is further configured to send a read request for requesting to read the first type of data to the memory controller [3, Fig 1] through the interface [Fig 1; The line showing a data connection between host 4 and controller 3 shows there is an interface on host that the connection connects to] when the operating system is initiated, wherein the read request indicates to read the first type of data from the first type of memory cell [S16, Fig 13; Fig 14; Paragraphs 0033, 0037, 0041, and 0048; Data that is written into the SLC area is later read from the SLC area due to a read request from the host which would include the address of where to read the data from].
Regarding claim 17, Kantani teaches receiving a first write request [S1, S11, S12, and S13, Fig 12; A write that gets written in SLC is considered a first write request], wherein the first write request [S1, S11, S12, and S13, Fig 12] comprises a first type of data [S12 and S13; Data written to SLC is system data type of data]; and
labeling a first data tag for the first type of data in response to the first write request [S13, Fig 12; Fig 14; Paragraph 0038; Writing to SLC tags the system data with physical address information indicating the data is in SLC memory for later retrieval using the conversion table], wherein the first data tag indicates that the first type of data is stored in a first type of memory cell [SLC AREA, Fig 9; S13, Fig 12] in a memory device [2, Fig 1].
Regarding claim 18, Kantani teaches the first write request [S1, S11, S12, and S13, Fig 12] comprises a first identification bit, the first identification bit is marked as a first value, the first value represents a first request format corresponding to the first write request, and the first request format is a format set for the first type of data [IDENTIFICATION FLAG, Fig 10; Paragraphs 0076 – 0077; The identification flag is a bit that indicates if the data to be written is either system data or not system data].
Regarding claim 19, Kantani teaches the labeling the first data tag for the first type of data in response to the first write request [S13, Fig 12; Fig 14; Paragraph 0038; Writing to SLC tags the system data with physical address information indicating the data is in SLC memory for later retrieval using the conversion table] comprises labeling the first data tag for the first type of data based on the first value of the first identification bit [IDENTIFICATION FLAG, Fig 10; S13, Fig 12; Fig 14; Paragraphs 0038 and 0076 - 0077; The physical address assigned to data is based on the identification flag].
Regarding claim 20, Kantani teaches receiving a second write request, wherein the second write request comprises a second type of data [S1, S11, S12, and S14; Paragraph 0080; A write to the QLC area shows the data is of a second type that is not system data]; and
writing the second type of data into the first type of memory cell or a second type of memory cell [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080] in the memory device [2, Fig 1] in response to the second write request [S1, S11, S12, and S14; Paragraph 0080], wherein the first type of memory cell [SLC AREA, Fig 9; S13, Fig 12] is configured to be capable of being written with N-bit data, the second type of memory cell is configured to be capable of being written with M-bit data, and N is less than M [QLC AREA, Fig 9; S14, Fig 12; Paragraph 0080; SLC writes 1 bit of data per cell where QLC writes more then one bit of memory per cell].
Conclusion
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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