DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-7, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma (US2022/0385853).
Regarding claim 1, Ma discloses an image sensor comprising (figures 1, 5): a first layer having a plurality of pixels (sensor die 282); a second layer (logic die 280) having a peripheral circuit, the peripheral circuit being connected with the plurality of pixels through a plurality of row lines and a plurality of column lines, the peripheral circuit being configured to drive the plurality of pixels, and the second layer being stacked on the first layer in a first direction; wherein each pixel of the plurality of pixels includes a photodiode (PPD), a floating diffusion region (FD) configured to store charge generated by the photodiode (PPD), a transfer transistor (TG) connected with a space between the photodiode (PPD) and the floating diffusion region (FD), and an amplification transistor (SF) connected with the floating diffusion region, wherein the first layer includes a first substrate (184), a first interlayer insulating layer (oxide) positioned on a surface of the first substrate (184), a semiconductor layer (177) positioned on a portion of the surface of the first substrate (184), and a first insulating layer positioned (oxide) between the first substrate (184) and the semiconductor layer (177), wherein a source region (Src), a drain region (Drain), and a channel region (Chan) of the amplification transistor (SF) are positioned in the semiconductor layer (177), and wherein the channel region (Chan) of the amplification transistor (SF) is positioned in a portion of the semiconductor layer (177) overlapping the floating in the first direction.
Regarding claim 2, Ma discloses the image sensor of claim 1, wherein a gate of the transfer transistor is a vertical transfer gate (Fig. 1: See vertical TR).
Regarding claim 4, Ma discloses the image sensor of claim 1, wherein the semiconductor layer (Fig. 2-3: 177) includes an amorphous oxide semiconductor (Fig. 2-3: Oxide).
Regarding claim 6, Ma discloses the image sensor of claim 1, wherein the semiconductor layer includes amorphous silicon or polysilicon ([0009]).
Regarding claim 7, Ma discloses the image sensor of claim 1, wherein each pixel of the plurality of pixels includes a selection transistor (RS: [0011]) connected with a space between the amplification transistor (SF) and a column line ([0011]).
Regarding claim 13, Ma discloses the image sensor of claim 12, wherein the reset transistor is connected with a space between the first power node and the first node (Fig. 1: See RST/ 139 that connect with a space between VDD and iSF or FD; [0013]).
Regarding claim 15, Ma discloses the image sensor of claim 1, wherein a portion of the semiconductor layer, adjacent to the floating diffusion region (FD), has a fin structure (Fig. 2-4: See fin structures in substrate 184 or STI adjacent to FD).
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US2022/0384512).
Regarding claim 1, Lee discloses an image sensor comprising (figures 1, 2C, 7A, [0030], [0038], [0046]): a first layer (100-1) having a plurality of pixels; and
a second layer (100-2) having a peripheral circuit, the peripheral circuit being connected with the plurality of pixels through a plurality of row lines and a plurality of column lines, the peripheral circuit being configured to drive the plurality of pixels, and
the second layer (100-2) being stacked on the first layer in a first direction, wherein each pixel of the plurality of pixels includes a photodiode (PD),
a floating diffusion region (FD) configured to store charge generated by the photodiode (PD), a transfer transistor (TX) connected with a space between the photodiode (PD) and the floating diffusion region (FD, 170), and
an amplification transistor (SFX, 160-3) connected with the floating diffusion region (170), wherein the first layer includes a first substrate (101), a first interlayer insulating layer (SS) positioned on a surface of the first substrate (101),
a semiconductor layer (160) positioned on a portion of the surface of the first substrate (SUB), and a first insulating layer positioned (140) between the first substrate (101) and the semiconductor layer (160), wherein a source region, a drain region, and a channel region of the amplification transistor (SFX, 160-3) are positioned in the semiconductor layer (160), and wherein the channel region (150C-3) of the amplification transistor (SFX) is positioned in a portion of the semiconductor layer (160) overlapping the floating diffusion region (FD, 170) in the first direction.
Regarding claim 2, Ma discloses the image sensor of claim 1, wherein a gate of the transfer transistor is a vertical transfer gate (Fig. 1: See vertical TX).
Regarding claim 3, Lee discloses the image sensor of claim 2, wherein the photodiode is disposed below the floating diffusion region in the first direction (claim 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Lee (US2016/0056301).
Claim 5 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma in view of Gardner (US2023/0253452).
Regarding claim 5, Ma fails to disclose the image sensor of claim 1, wherein the semiconductor layer includes a 2D nanomaterial.
In an analogous of art, Gardner teaches formation of semiconductor devices made using 3D nano sheets with 2D materials transistor channels. The semiconductor devices can be manufactured using epitaxial growth techniques and by using different SixGei-x (where X is equal to mole fraction) material layers for highly conductive transistor channels using 2D materials. In light of the teaching from Gardner, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include nano sheet material. The modifications thus utilize material layers for highly conductive transistor channels using 2D materials (Gardner: [0016-0023]).
Allowable Subject Matter
Claims 8, 10-11 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach the image sensor of claim 8 further in combination with: “wherein a source region and a drain region of the selection transistor are positioned in the semiconductor layer, and a gate of the selection transistor is positioned on the semiconductor layer”.
Regarding claim 10, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach the image sensor of claim 7 further in combination with: “wherein a source region and a drain region of the selection transistor are positioned in the first substrate, and a gate of the selection transistor is positioned on the first insulating layer”.
Regarding claim 11, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach the image sensor of claim 7 further in combination with: “ wherein each pixel of the plurality of pixels includes a reset transistor connected with a space between the floating diffusion region and a first power node, the amplification transistor is connected with a space between the floating diffusion region and a second power node, and a source region and a drain region of the reset transistor are positioned in the first substrate, and a gate of the selection transistor is positioned on the first insulating layer”.
Regarding dependent claims 9 and 12, the claims are objected as being depending upon the objected claims 8 and 11, respectively.
Regarding claim 14, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach the image sensor of claim 1 further in combination with: “wherein each pixel of the plurality of pixels includes a back gate to which a negative voltage is applied, the back gate overlaps the floating diffusion region and a portion of the semiconductor layer in the first direction, and the portion of the semiconductor layer includes the channel region of the amplification transistor”.
Regarding independent claim 16, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach: “a first layer having a plurality of pixels; and a second layer having a peripheral circuit, the peripheral circuit being configured to obtain a pixel signal based on driving the plurality of pixels, and the second layer being stacked on the first layer in a first direction, wherein each pixel of the plurality of pixels includes a photodiode, a floating diffusion region configured to store charge generated by the photodiode, a transfer transistor connected with a space between the photodiode and the floating diffusion region, an amplification transistor connected with the floating diffusion region, and a selection transistor connected with a space between the amplification transistor and a column line, wherein the first layer includes a first substrate, a first interlayer insulating layer positioned on a surface of the first substrate, a semiconductor layer positioned on a portion of the surface of the first substrate, and a first insulating layer positioned between the first substrate and the semiconductor layer, wherein a gate of the transfer transistor and the floating diffusion region are disposed in a second direction, the semiconductor layer extends in a third direction, and the second direction intersects the third direction, and wherein the second direction and the third direction are parallel to an upper surface of the first substrate, and the second direction and the third direction are perpendicular to the first direction", in combination with all other limitations of the claim.
Regarding dependent claims 17-19, the claims are allowed as being depending upon the allowed claim 16, respectively.
Regarding independent claim 20, the prior art of Ma discloses an amplifier transistor within an image-sensor pixel that is implemented upside down relative to conventional orientation. The prior art of Lee discloses active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate. The prior art of Masuoka (US2013/0069149) discloses a pixel selection line metal layer (17a), which is connected to an upper semiconductor region and a pixel selection line conductor layer (14) through two contact holes. The prior art of Go (US2024/0178253) discloses an active region comprising a source region and a drain region, a source follower gate pattern on the active region, the drain region being adjacent to a first side surface of the source follower gate pattern, the source region being adjacent to a second side surface of the source follower gate pattern, and a gate insulating layer between the active region and the source follower gate pattern. The prior art of Takahashi (US2021/0074747) discloses an isolation structure (810a,810b) that extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. Thus, while many references teach pixel structures with drain region, source follower and other gate patterns, none of the references alone or in combination, provide a motivation to teach:, none of the references alone or in combination, provide a motivation to teach: “: a first layer having a plurality of pixels; and a second layer having a peripheral circuit, the peripheral circuit being configured to obtain a pixel signal based on driving the plurality of pixels, and the second layer being stacked on the first layer in a first direction, wherein each pixel of the pixels includes a photodiode, a floating diffusion region configured to store charge generated by the photodiode, a transfer transistor connected with a space between the photodiode and the floating diffusion region, a reset transistor connected with a space between the floating diffusion region and a first power node, an amplification transistor connected with a space between the floating diffusion region, and a selection transistor connected with a space between the amplification transistor and a column line, wherein the first layer includes a first substrate, a first interlayer insulating layer 5 positioned on a surface of the first substrate, a semiconductor layer positioned on a portion of the surface of the first substrate, and a first insulating layer positioned between the first substrate and the semiconductor layer, wherein the photodiode, the floating diffusion region, an active region of the transfer transistor, and an active region of the reset transistor are positioned in the first substrate, wherein a channel region of the amplification transistor is positioned in a portion of the semiconductor layer disposed on the floating diffusion region, and a gate of the amplification transistor is positioned as the floating diffusion region, and wherein a gate of the transfer transistor is a vertical transfer gate, and the photodiode is disposed below the floating diffusion region in the first direction", in combination with all other limitations of the claim.
Conclusion
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/HUNG H LAM/Primary Examiner, Art Unit 2639 06/27/26
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